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PDF LC420EUG-RDV2 Data sheet ( Hoja de datos )

Número de pieza LC420EUG-RDV2
Descripción WUXGA TFT LCD
Fabricantes RAKEN 
Logotipo RAKEN Logotipo



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No Preview Available ! LC420EUG-RDV2 Hoja de datos, Descripción, Manual

Product Specification
SPECIFICATION
FOR
APPROVAL
LC420EUG
( ) Preliminary Specification
( ) Final Specification
Title
42.0” WUXGA TFT LCD
BUYER
MODEL
LGE
SUPPLIER
RAKEN Co., Ltd.
*MODEL
LC420EUG
SUFFIX
RDV2
*When you obtain standard approval,
please use the above model name without suffix
APPROVED BY
/
SIGNATURE
DATE
APPROVED BY
Charlie.Ko/ Team Leader
SIGNATURE
DATE
REVIEWED BY
/ Power.Zheng/ Engineer
/
Please return 1 copy for your confirmation with
your signature and comments.
Ver. 1.0
PREPARED BY
Suxi.Jiang/ Engineer
TV R&D LCM Qualification Dept.
RAKEN Co., Ltd.
0 /35

1 page




LC420EUG-RDV2 pdf
Product Specification
LC420EUG
1. General Description
The LC420EUG is a Color Active Matrix Liquid Crystal Display with an integral the Source PCB and Gate
implanted on Panel (GIP). The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive type display operating in the normally black mode. It has a 42.02 inch diagonally measured
active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 8-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 16.7M(true) colors.
It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut,
high color depth and fast response time are important.
Power (VCC,VDD,HVDD,VGH,VGL)
Source Control Signal
Gate Control Signal
Gamma Reference Voltage
CN1
(60pin)
mini-LVDS (RGB) for Left drive
Power (VCC,VDD,HVDD,VGH,VGL)
Source Control Signal
Gate Control Signal
Gamma Reference Voltage
CN2
(60pin)
mini-LVDS (RGB) for Right drive
S1
G1
Source Driver Circuit
S1920
TFT - LCD Panel
(1920 × RGB × 1080 pixels)
[Gate In Panel]
G1080
LED Anode
LED Cathode
CN1 (14pin)
H : 5Block
V : 2Block
Local Dimming : 10 Block
General Features
Active Screen Size
Outline Dimension
Pixel Pitch
Pixel Format
Color Depth
Luminance, White
Viewing Angle (CR>10)
Power Consumption
Weight
Display Operating Mode
Surface Treatment
42.02 inches(1067.31mm) diagonal
968.4(H) × 564(V) X 10.8(B)/18.3 mm(D) (Typ.)
0.4845 mm x 0.4845 mm
1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement
8bit, 16,7 M colors
360 cd/m2 (Center 1point ,Typ.)
Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))
Total 92.9W (TBD.) [Logic= 7.3W, LED Backlight=85.6W (Ext.PWM=100%)]
8.8 Kg (Typ.)
Transmissive mode, normally black
Hard coating(3H), Anti-glare treatment of the front polarizer (Haze 10%)
Ver. 1.0
4 /35

5 Page





LC420EUG-RDV2 arduino
Product Specification
LC420EUG
-LCD Connector (CN2): TF06L-60S-0.5SH(Manufactured by HRS)
Table 3-2. MODULE CONNECTOR(CN2) PIN CONFIGURATION
No Symbol
Description
No Symbol
Description
1
GMA 1 GAMMA VOLTAGE 1 (Output From LCD)
31
RLV1 + Right Mini LVDS Receiver Signal(1+)
2 GMA 3 GAMMA VOLTAGE 3
32 RLV0 - Right Mini LVDS Receiver Signal(0-)
3 GMA 4 GAMMA VOLTAGE 4
33 RLV0 + Right Mini LVDS Receiver Signal(0+)
4 GMA 5 GAMMA VOLTAGE 5
34
GND
Ground
5 GMA 7 GAMMA VOLTAGE 7
35
VCC
Logic Power Supply Voltage
6
GMA 9 GAMMA VOLTAGE 9 (Output From LCD)
36
VCC
Logic Power Supply Voltage
7 GMA 10 GAMMA VOLTAGE 10 (Output From LCD) 37
GND
Ground
8 GMA 12 GAMMA VOLTAGE 12
38 H_VDD Half Driver Power Supply Voltage
9 GMA 14 GAMMA VOLTAGE 14
39 H_VDD Half Driver Power Supply Voltage
10 GMA 15 GAMMA VOLTAGE 15
40
VDD
Driver Power Supply Voltage
11 GMA 16 GAMMA VOLTAGE 16
41
VDD
Driver Power Supply Voltage
12 GMA 18 GAMMA VOLTAGE 18 (Output From LCD) 42
GND
Ground
13
GND
Ground
43
GND
Ground
14 OPT_N “H” Normal Display / “L” Rotation Display
44 VCOM_R VCOM Right Input
15 H_CONV "H“ H 2dot Inversion/ "L" H 1dot Inversion
45 VCOM_R_FB VCOM Right Feed-Back Output
16
GSP
GATE Start Pulse
46 GIP_Reset GIP Reset
17
POL
Polarity Control Signal
47 VST VERTICAL START PULSE
18
SOE
Source Output Enable SIGNAL
48
VGL
GATE Low Voltage
19
GND
Ground
49 VGH_EVEN GIP Panel VDD for Even GATE TFT
20 NC No Connection
50 VGH_ODD GIP Panel VDD for Odd GATE TFT
21 NC No Connection
51 VGI_P GIP Bi-Scan (Normal =VGH Rotate = VGL)
22 NC No Connection
52 VGI_N GIP Bi-Scan (Normal =VGL Rotate = VGH)
23 NC No Connection
53 GCLK6 GIP GATE Clock 6
24 NC No Connection
54 GCLK5 GIP GATE Clock 5
25 NC No Connection
55 GCLK4 GIP GATE Clock 4
26 RCLK - Right Mini LVDS Receiver Clock Signal(-)
56 GCLK3 GIP GATE Clock 3
27 RCLK + Right Mini LVDS Receiver Clock Signal(+)
57 GCLK2 GIP GATE Clock 2
28 RLV2 - Right Mini LVDS Receiver Signal(2-)
58 GCLK1 GIP GATE Clock 1
29 RLV2 + Right Mini LVDS Receiver Signal(2+)
59 NC No Connection
30 RLV1 - Right Mini LVDS Receiver Signal(1-)
60 LTD_OUT LTD OUTPUT
Note :
1. Please refer to application note for details
(GIP & Gamma Voltage setting)
Source Right PCB
Ver. 1.0
CN 2
#1 #60
CN 1
#1 #60
Source Left PCB
10 /35

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