PDF MSC8256 Data sheet ( Hoja de datos )

Número de pieza	MSC8256
Descripción	Six-Core Digital Signal Processor
Fabricantes	Freescale Semiconductor
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Freescale Semiconductor Data Sheet Six-Core Digital Signal Processor Document Number: MSC8256 Rev. 6, 7/2013 MSC8256 FC-PBGA–783 29 mm × 29 mm • Six StarCore SC3850 DSP subsystems, each with an SC3850 DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, unified 512 Kbyte L2 cache configurable as M2 memory in 64 Kbyte increments, memory management unit (MMU), extended programmable interrupt controller (EPIC), two general-purpose 32-bit timers, debug and profiling support, low-power Wait, Stop, and power-down processing modes, and ECC/EDC support. • Chip-level arbitration and switching system (CLASS) that provides full fabric non-blocking arbitration between the cores and other initiators and the M2 memory, shared M3 memory, DDR SRAM controllers, device configuration control and status registers, and other targets. • 1056 Kbyte 128-bit wide M3 memory, 1024 Kbytes of which can be turned off to save power. • 96 Kbyte boot ROM. • Three input clocks (one global and two differential). • Five PLLs (three global and two Serial RapidIO PLLs). • Two DDR controllers with up to a 400 MHz clock (800 MHz data rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to four banks (two per controller) and support for DDR2 and DDR3. • DMA controller with 32 unidirectional channels supporting 16 memory-to-memory channels with up to 1024 buffer descriptors per channel, and programmable priority, buffer, and multiplexing configuration. It is optimized for DDR SDRAM. • Up to four independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion, up to 62.5 Mbps data rate for each TDM link, and with glueless interface to E1 or T1 framers that can interface with H-MVIP/H.110 devices, TSI, and codecs such as AC-97. • High-speed serial interface that supports two Serial RapidIO interfaces, one PCI Express interface, and two SGMII interfaces (multiplexed). The Serial RapidIO interfaces support 1x/4x operation up to 3.125 Gbaud with a single messaging unit and two DMA units. The PCI Express controller supports 32- and 64-bit addressing, x4, x2, and x1 link. • QUICC Engine technology subsystem with dual RISC processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction RAM, supporting two communication controllers for two Gigabit Ethernet interfaces (RGMII or SGMII), to offload scheduling tasks from the DSP cores, and an SPI. • I/O Interrupt Concentrator consolidates all chip maskable interrupt and non-maskable interrupt sources and routes then to INT_OUT, NMI_OUT, and the cores. • UART that permits full-duplex operation with a bit rate of up to 6.25 Mbps. • Two general-purpose 32-bit timers for RTOS support per SC3850 core, four timer modules with four 16-bit fully programmable timers, and eight software watchdog timers (SWT). • Eight programmable hardware semaphores. • Up to 32 virtual interrupts and a virtual NMI asserted by simple write access. • I2C interface. • Up to 32 GPIO ports, sixteen of which can be configured as external interrupts. • Boot interface options include Ethernet, Serial RapidIO interface, I2C, and SPI. • Supports standard JTAG interface • Low power CMOS design, with low-power standby and power-down modes, and optimized power-management circuitry. • 45 nm SOI CMOS technology. © 2008–2013 Freescale Semiconductor, Inc. All rights reserved. 1 page 1.2 Signal List By Ball Location Table 1 presents the signal list sorted by ball number. When designing a board, make sure that the power rail for each signal is appropriately considered. The specified power rail must be tied to the voltage level specified in this document if any of the related signal functions are used (active) Note: The information in Table 1 and Table 2 distinguishes among three concepts. First, the power pins are the balls of the device package used to supply specific power levels for different device subsystems (as opposed to signals). Second, the power rails are the electrical lines on the board that transfer power from the voltage regulators to the device. They are indicated here as the reference power rails for signal lines; therefore, the actual power inputs are listed as N/A with regard to the power rails. Third, symbols used in these tables are the names for the voltage levels (absolute, recommended, and so on) and not the power supplies themselves. Table 1. Signal List by Ball Number Ball Number A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 B1 B2 B3 B4 B5 B6 M2DQS3 M2DQS3 M2ECC0 M2DQS8 M2DQS8 M2A5 M2CK1 M2CK1 M2CS0 M2BA0 M2CAS M2DQ34 M2DQS4 M2DQS4 M2DQ50 M2DQS6 M2DQS6 M2DQ48 M2DQ49 VSS Reserved SXPVDD1 SXPVSS1 Reserved Reserved SXCVDD1 SXCVSS1 M2DQ24 GVDD2 M2DQ25 VSS GVDD2 M2ECC1 Signal Name1,2 Pin Type10 I/O I/O I/O I/O I/O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O Ground NC Power Ground NC NC Power Ground I/O Power I/O Ground Power I/O Power Rail Name GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 N/A — N/A N/A — — N/A N/A GVDD2 N/A GVDD2 N/A N/A GVDD2 Freescale Semiconductor MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6 5 5 Page Ball Number J26 J27 J28 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 SXCVSS1 SXCVDD1 SXCVSS1 VSS GVDD2 M2DM1 VSS GVDD2 M2DQ0 VSS GVDD2 M2DQ5 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD Reserved Reserved Reserved SXPVDD2 SXPVSS2 SXCVDD2 SXCVSS2 SXCVDD2 SXCVSS2 M2DQ9 M2DQ12 M2DQ13 M2DQS0 M2DQS0 M2DM0 M2DQ3 M2DQ2 M2DQ4 VDD VSS M3VDD Table 1. Signal List by Ball Number (continued) Signal Name1,2 Pin Type10 Ground Power Ground Ground Power O Ground Power I/O Ground Power I/O Ground Power Ground Power Ground Power Ground Power Ground Power NC NC NC Power Ground Power Ground Power Ground I/O I/O I/O I/O I/O O I/O I/O I/O Power Ground Power Power Rail Name N/A N/A N/A N/A N/A GVDD2 N/A N/A GVDD2 N/A N/A GVDD2 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A — — — N/A N/A N/A N/A N/A N/A GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 GVDD2 N/A N/A N/A Freescale Semiconductor MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 6 11 11 Page

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