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PDF RM0008 Data sheet ( Hoja de datos )

Número de pieza RM0008
Descripción Reference manual
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RM0008
Reference manual
STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and
STM32F107xx advanced ARM®-based 32-bit MCUs
Introduction
This reference manual targets application developers. It provides complete information on
how to use the STM32F101xx, STM32F102xx, STM32F103xx and
STM32F105xx/STM32F107xx microcontroller memory and peripherals. The STM32F101xx,
STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx will be referred to as
STM32F10xxx throughout the document, unless otherwise specified.
The STM32F10xxx is a family of microcontrollers with different memory sizes, packages
and peripherals.
For ordering information, mechanical and electrical device characteristics please refer to the
low-, medium-, high- and XL-density STM32F101xx and STM32F103xx datasheets, to the
low- and medium-density STM32F102xx datasheets and to the
STM32F105xx/STM32F107xx connectivity line datasheet.
For information on programming, erasing and protection of the internal Flash memory
please refer to:
• PM0075, the Flash programming manual for low-, medium- high-density and
connectivity line STM32F10xxx devices
• PM0068, the Flash programming manual for XL-density STM32F10xxx devices.
For information on the ARM® Cortex®-M3 core, please refer to the STM32F10xxx Cortex®-
M3 programming manual (PM0056).
Related documents
Available from www.st.com:
• STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx/STM32F107xx and
datasheets
• STM32F10xxx Cortex®-M3 programming manual (PM0056)
• STM32F10xxx Flash programming manual (PM0075)
• STM32F10xxx XL-density Flash programming manual (PM0068)
June 2014
DocID13902 Rev 15
1/1128
www.st.com

1 page




RM0008 pdf
Contents
RM0008
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.3.10
8.3.11
8.3.12
8.3.13
Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 134
Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 141
APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . 142
AHB Peripheral Clock enable register (RCC_AHBENR) . . . . . . . . . . . 145
APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 146
APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . 148
Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 150
Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
AHB peripheral clock reset register (RCC_AHBRSTR) . . . . . . . . . . . . 153
Clock configuration register2 (RCC_CFGR2) . . . . . . . . . . . . . . . . . . . 154
RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
9 General-purpose and alternate-function I/Os (GPIOs and AFIOs) . . 159
9.1 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
9.1.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
9.1.2 Atomic bit set or reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
9.1.3 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
9.1.4 Alternate functions (AF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
9.1.5 Software remapping of I/O alternate functions . . . . . . . . . . . . . . . . . . 162
9.1.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
9.1.7 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
9.1.8 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
9.1.9 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
9.1.10 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
9.1.11 GPIO configurations for device peripherals . . . . . . . . . . . . . . . . . . . . . 166
9.2 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
9.2.1 Port configuration register low (GPIOx_CRL) (x=A..G) . . . . . . . . . . . . 171
9.2.2 Port configuration register high (GPIOx_CRH) (x=A..G) . . . . . . . . . . . 172
9.2.3 Port input data register (GPIOx_IDR) (x=A..G) . . . . . . . . . . . . . . . . . . 172
9.2.4 Port output data register (GPIOx_ODR) (x=A..G) . . . . . . . . . . . . . . . . 173
9.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..G) . . . . . . . . . . . . . . . 173
9.2.6 Port bit reset register (GPIOx_BRR) (x=A..G) . . . . . . . . . . . . . . . . . . . 174
9.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..G) . . . . . . . . . . 174
9.3 Alternate function I/O and debug configuration (AFIO) . . . . . . . . . . . . . 175
9.3.1 Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15 . . . . 175
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RM0008 arduino
Contents
RM0008
14.4
TIM1&TIM8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
14.4.1 TIM1&TIM8 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . 333
14.4.2 TIM1&TIM8 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . 334
14.4.3 TIM1&TIM8 slave mode control register (TIMx_SMCR) . . . . . . . . . . . 337
14.4.4 TIM1&TIM8 DMA/interrupt enable register (TIMx_DIER) . . . . . . . . . . 339
14.4.5 TIM1&TIM8 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . 341
14.4.6 TIM1&TIM8 event generation register (TIMx_EGR) . . . . . . . . . . . . . . 342
14.4.7 TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . . . . 344
14.4.8 TIM1&TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . . . . 347
14.4.9 TIM1&TIM8 capture/compare enable register (TIMx_CCER) . . . . . . . 348
14.4.10 TIM1&TIM8 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
14.4.11 TIM1&TIM8 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
14.4.12 TIM1&TIM8 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . 351
14.4.13 TIM1&TIM8 repetition counter register (TIMx_RCR) . . . . . . . . . . . . . . 352
14.4.14 TIM1&TIM8 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . 352
14.4.15 TIM1&TIM8 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . 353
14.4.16 TIM1&TIM8 capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . 353
14.4.17 TIM1&TIM8 capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . 354
14.4.18 TIM1&TIM8 break and dead-time register (TIMx_BDTR) . . . . . . . . . . 354
14.4.19 TIM1&TIM8 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . 356
14.4.20 TIM1&TIM8 DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . 357
14.4.21 TIM1&TIM8 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
15 General-purpose timers (TIM2 to TIM5) . . . . . . . . . . . . . . . . . . . . . . . . 360
15.1 TIM2 to TIM5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
15.2 TIMx main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
15.3 TIMx functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
15.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
15.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
15.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
15.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
15.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
15.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
15.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
15.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
15.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
15.3.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
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