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PDF SiI161B Data sheet ( Hoja de datos )
| Número de pieza | SiI161B | |
| Descripción | PanelLink Receiver | |
| Fabricantes | Silicon Image | |
| Logotipo |  |
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®
Technology
SiI 161B
PanelLink Receiver
Data Sheet
Document # SiI-DS-0038-C
1 page  
SiI 161B PanelLink® Receiver
Data Sheet
General Description
The SiI 161B receiver uses PanelLink Digital
technology to support high-resolution displays up to
UXGA (25-165MHz). This receiver supports up to true
color panels (24 bits per pixel, 16M colors) with both
one and two pixels per clock.
All PanelLink products are designed on a scaleable
CMOS architecture, ensuring support for future
performance enhancements while maintaining the
same logical interface. System designers can be
assured that the interface will be stable through a
number of technology and performance generations.
PanelLink Digital technology simplifies PC and display
interface design by resolving many of the system level
issues associated with high-speed mixed signal design,
providing the system designer with a digital interface
solution that is quicker to market and lower in cost.
SiI 161B Pin Diagram
August 2002
Features
• Low Power Operation: 280mA max. current
consumption at 3.3V core operation
• Time staggered data output for reduced ground
bounce and lower EMI
• Sync Detect feature for Plug & Display
• Cable Distance Support: over 5m with twisted-
pair, fiber-optics ready
• ESD tolerant to 5kV (HBM on all pins)
• Compliant with DVI 1.0 (DVI is backwards
compatible with VESA® P&DTM, FPDI-2TM and
DFP)
• HSYNC de-jitter circuitry enables stable operation
even when HSYNC contains jitter
• Low power standby mode
• Automatic entry into standby mode with clock
detect circuitry
• Standard and Pb-free packages (see page 25).
Figure 1. Pin Diagram for SiI 161B
1
SiI-DS-0038-C
5 Page 
SiI 161B PanelLink Receiver
Data Sheet
Timing Diagrams
2.0 V
2.0 V
SiI 161B
10pF/ 5pF
0.8 V
DLHT
Figure 3. Digital Output Transition Times
Note:
1. 10pF loading used at ST=1 and 5pF loading using at ST=0
0.8 V
DHLT
2.0 V
RCIH
RCIP
2.0 V
2.0 V
0.8 V
0.8 V
RCIL
Figure 4. Receiver Clock Cycle/High/Low Times
RX0
RX1
RX2
VDIFF=0V
TCCS
VDIFF=0V
Figure 5. Channel-to-Channel Skew Timing
7 SiI-DS-0038-C
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SiI161B.PDF ] | |
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