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PDF SiI163B Data sheet ( Hoja de datos )
| Número de pieza | SiI163B | |
| Descripción | PanelLink Receiver | |
| Fabricantes | Silicon Image | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SiI163B (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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®
Technology
SiI 163B
PanelLink Receiver
Data Sheet
Document # SiI-DS-0055-C
1 page  
SiI 163B PanelLink® Receiver
Data Sheet
General Description
The SiI 163B receiver uses PanelLink Digital
technology to support high-resolution (24 bit/pixel, 16M
colors) displays up to UXGA and beyond, with dual-link
DVI for a total bandwidth up to 330 megapixels per
second.
All PanelLink products are designed on a scaleable
CMOS architecture, ensuring support for future
performance enhancements while maintaining the
same logical interface. System designers can be
assured that the interface will be stable through a
number of technology and performance generations.
PanelLink Digital technology simplifies PC and display
interface design by resolving many of the system level
issues associated with high-speed mixed signal
design, providing the system designer with a digital
interface solution that is quicker to market and lower in
cost.
SiI 163B Pin Diagram
CONTROLS
GPO
Features
July 2005
• Low Power Operation: 280mA max. current
consumption at 3.3V core operation
• Sync Detect feature for Plug & Display
“Hot Plugging”
• Cable Distance Support: over 5m with twisted-
pair, fiber-optics ready
• Compliant with DVI 1.0
• Low power standby mode
• Automatic entry into standby mode with clock
detect circuitry
• Dual-Link DVI support with two devices
configured as master and slave
EVEN 8-bits RED
QO2
QO3
QO4
QO5
QO6
QO7
OVCC
OGND
QO8
QO9
QO10
QO11
QO12
QO13
QO14
QO15
VCC
GND
QO16
QO17
QO18
QO19
QO20
QO21
QO22
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
SiI 163B
100 -Pin TQFP
(Top View)
25 QE13
24 QE12
23 QE11
22 QE10
21 QE9
20 QE8
19 OGND
18 OVCC
17 QE7
16 QE6
15 QE5
14 QE4
13 QE3
12 QE2
11 QE1
10 QE0
9 PDO#
8 SCDT
7 STAG_OUT#/SYNC
6 VCC
5 GND
4 PIXS/M_S
3 ST
2 PD#
1 S_D
DIFFERENTIAL SIGNAL
PLL
SiI-DS-0055-C
5 Page 
SiI 163B PanelLink Receiver
Data Sheet
Timing Diagrams
2.0 V
2.0 V
SiI 163B
10pF/ 5pF
0.8 V
DLHT
Figure 2. Digital Output Transition Times
Note:
1. 10pF loading used at ST=1 and 5pF loading using at ST=0
0.8 V
DHLT
2.0 V
RCIH
RCIP
2.0 V
2.0 V
0.8 V
0.8 V
RCIL
Figure 3. Receiver Clock Cycle/High/Low Times
RX0
RX1
RX2
VDIFF=0V
TCCS
VDIFF=0V
Figure 4. Channel-to-Channel Skew Timing
7 SiI-DS-0055-C
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SiI163B.PDF ] | |
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