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PDF M95320-R Data sheet ( Hoja de datos )
| Número de pieza | M95320-R | |
| Descripción | 32 Kbit and 64 Kbit Serial SPI bus EEPROMs | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M95320 M95320-W M95320-R
M95640 M95640-W M95640-R
32 Kbit and 64 Kbit Serial SPI bus EEPROMs
with high speed clock
Feature summary
■ Compatible with SPI Bus Serial Interface
(Positive Clock SPI Modes)
■ Single Supply Voltage:
– 4.5 to 5.5V for M95320 and M95640
– 2.5 to 5.5V for M95320-W and M95320-W
– 1.8 to 5.5V for M95320-R and M95640-R
■ 10MHz, 5MHz or 2MHz clock rates
■ 5ms or 10ms Write Time
■ Status Register
■ Hardware Protection of the Status Register
■ Byte and Page Write (up to 32 Bytes)
■ Self-Timed Programming Cycle
■ Adjustable Size Read-Only EEPROM Area
■ Enhanced ESD Protection
■ More than 1 million Write cycles
■ More than 40-Year Data Retention
■ Packages
– ECOPACK® (RoHS compliant)
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
MLP8 (MB)
2x3 mm
July 2006
Rev 6
1/44
www.st.com
1
1 page  
M95320, M95640, M95320-x, M95640-x
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Serial Input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
SO8N – 8 lead Plastic Small Outline, 150 mils body width, package outline . . . . . . . . . . . 38
TSSOP8 – 8 lead Thin Shrink Small Outline, package outline . . . . . . . . . . . . . . . . . . . . . . 39
MLP8 - 8-lead Ultra thin Fine pitch Dual Flat No Lead, package outline . . . . . . . . . . . . . . 40
5/44
5 Page 
M95320, M95640, M95320-x, M95640-x
4 Operating features
Operating features
4.1
4.1.1
4.1.2
4.1.3
Supply voltage (VCC)
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 8.). In order to
secure a stable DC supply voltage, it is recommended to decouple the VCC line with a
suitable capacitor (usually of the order of 10nF to 100nF) close to the VCC/VSS package
pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (tW).
Power-up conditions
When the power supply is turned on, VCC rises from VSS to VCC. During this time, the Chip
Select (S) is not allowed to float but must follow the VCC voltage, therefore the S line should
be connected to VCC via a suitable pull-up resistor.
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge
sensitive as well as level sensitive: after Power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been High, prior to going Low to start the first operation.
The VCC rise time must not be faster than 1V/µs.
Internal device Reset
In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR)
circuit is included. At Power-up (continuous rise of VCC), the device will not respond to any
instruction until VCC has reached the Power On Reset threshold voltage (this threshold is
lower than the minimum VCC operating voltage defined in Tables XX).
When VCC has passed the POR threshold, the device is reset and in the following state:
● Standby Power mode
● deselected (at next Power-up, a falling edge is required on Chip Select (S) before any
instructions can be started).
● not in the Hold Condition
Status Register state:
● the Write Enable Latch (WEL) is reset to 0
● Write In Progress (WIP) is reset to 0. The SRWD, BP1 and BP0 bits of the Status
Register are in the same state as when the power was last removed (they are non-
volatile bits).
11/44
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M95320-R.PDF ] | |
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