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TC58NVG4D2FTA00 fiches techniques PDF

Toshiba - 16 GBIT (4G x 8 BIT) CMOS NAND E2PROM

Numéro de référence TC58NVG4D2FTA00
Description 16 GBIT (4G x 8 BIT) CMOS NAND E2PROM
Fabricant Toshiba 
Logo Toshiba 





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TC58NVG4D2FTA00 fiche technique
TOSHIBA CONFIDENTIAL TC58NVG4D2FTA00
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
16 GBIT (4G × 8 BIT) CMOS NAND E2PROM (Multi-Level-Cell)
DESCRIPTION
The TC58NVG4D2 is a single 3.3 V 16 Gbit (18,367,119,360 bits) NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E2PROM) organized as (8192 + 448) bytes × 128 pages × 2076 blocks.
The device has two 8640-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 8640-byte increments. The Erase operation is implemented in a single block
unit (1 Mbytes + 56 Kbytes: 8640 bytes × 128 pages).
The TC58NVG4D2 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
Organization
Memory cell array
Register
Page size
Block size
TC58NVG4D2F
8640 × 259.5K × 8
8640 × 8
8640 bytes
(1M + 56 K) bytes
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Program, Multi Block Erase, Multi Page Copy, Mullti Page Read
Mode control
Serial input/output
Command control
Number of valid blocks
Min 1968 blocks
Max 2076 blocks
Power supply
VCC = 2.7 V to 3.6 V
Access time
Cell array to register 250 µs max
Serial Read Cycle
25 ns min
Program/Erase time
Auto Page Program
Auto Block Erase
1600 µs/page typ.
4 ms/block typ.
Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
TBD ( 50 mA max.)
TBD ( 50 mA max.)
TBD ( 50 mA max.)
100 µA max
Package
(Weight: TBD g typ.)
FOR RELIABILITY GUIDANCE, PLEASE REFER TO THE APPLICATION NOTES AND COMMENTS (17).
24 bit ECC for each 1024 bytes is required.
1 Rev 1.2 2009-09-14C

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