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PDF Si8050 Data sheet ( Hoja de datos )
| Número de pieza | Si8050 | |
| Descripción | 1 KV THREE TO SIX-CHANNEL DIGITAL ISOLATORS | |
| Fabricantes | Silicon Laboratories | |
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Si80xx-1kV
1 KV THREE TO SIX-CHANNEL DIGITAL ISOLATORS
Features
High-speed operation
Default high or low output
DC to 10 Mbps
Precise timing (typical)
No start-up initialization required 40 ns propagation delay
Wide Operating Supply Voltage
20 ns pulse width distortion
3.15 – 5.5 V
100 ns minimum pulse width
Up to 1000 VRMS isolation
Transient Immunity 50 kV/µs
High electromagnetic immunity AEC-Q100 qualification
Low power consumption (typical) Wide temperature range
2.3 mA per channel at 10 Mbps
–40 to 125 °C
Tri-state outputs with ENABLE RoHS-compliant packages
Schmitt trigger inputs
QSOP-16
Applications
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Description
Isolated ADC, DAC
Power inverters
Communication systems
Silicon Lab's family of low-power digital isolators are CMOS devices
offering substantial data rate, propagation delay, power, size, reliability,
and external BOM advantages over legacy isolation technologies. The
operating parameters of these products remain stable across wide
temperature ranges and throughout device service life for ease of
design and highly uniform performance. All device versions have
Schmitt trigger inputs for high noise immunity and only require VDD
bypass capacitors. Data rates up to 10 Mbps are supported, and all
devices achieve propagation delays of less than 65 ns. Enable inputs
provide a single point control for enabling and disabling output drive.
Ordering options include a choice of 1kVRMS isolation ratings.
Ordering Information:
See page 18.
Rev. 1.0 1/14
Copyright © 2014 by Silicon Laboratories
Si80xx-1kV
1 page  
Si80xx
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.15 to 5.5 V, VDD2 = 3.15 to 5.5 V, TA = –40 to 125 ºC)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Supply Current (10 Mbps)
VDD1
VDD2
Maximum Data Rate
VI = 5 MHz
CL = 15 pF
— 4.4 7.5 mA
— 9.4 12 mA
0 — 10 Mbps
Minimum Pulse Width
— — 100 ns
Propagation Delay
Pulse Width Distortion
|tPLH – tPHL|
Propagation Delay Skew2
Channel-Channel Skew
Output Rise Time
tPHL, tPLH
PWD
tPSK(P-P)
tPSK
tr
See Figure 2
See Figure 2
CL = 15 pF
See Figure 2
20 40 65 ns
— 20 30 ns
— 20 30 ns
— 20 30 ns
— 2.5 4.0 ns
Output Fall Time
tf CL = 15 pF
See Figure 2
— 2.5 4.0 ns
Common Mode
Transient Immunity
CMTI
VI = VDD or 0 V
VCM = 1500 V (see Figure 3)
35
50 — kV/µs
Enable to Data Valid
ten1
See Figure 1
— 10 — ns
Enable to Data Tri-State
Start-up Time3
ten2
tSU
See Figure 1
— 10 — ns
— 40 — µs
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
ENABLE
OUTPUTS
ten1 ten2
Figure 1. ENABLE Timing Diagram
Rev. 1.0
5
5 Page 
Si80xx
3.1. Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following
this, the outputs follow the states of inputs.
3.2. Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when VDD is below its specified operating circuits range. Both Side A and Side B each have their own
undervoltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A
unconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when VDD1 rises above
VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply. See Figure 5 for more details.
UVLO+
UVLO-
VDD1
UVLO+
UVLO-
VDD2
INPUT
tSTART
OUTPUT
tSD tSTART
tSTART
tPHL tPLH
Figure 5. Device Behavior during Normal Operation
Rev. 1.0
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet Si8050.PDF ] | |
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