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PDF PIC24FJ64GB110 Data sheet ( Hoja de datos )
| Número de pieza | PIC24FJ64GB110 | |
| Descripción | 16-Bit Flash Microcontrollers | |
| Fabricantes | Microchip Technology | |
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PIC24FJ256GB110 Family
Data Sheet
64/80/100-Pin,
16-Bit Flash Microcontrollers
with USB On-The-Go (OTG)
www.DataSheet4U.com
© 2008 Microchip Technology Inc.
Preliminary
DS39897B
1 page  
Pin Diagram (64-Pin TQFP)
PIC24FJ256GB110 FAMILY
PMD5/CN63/RE5
PMD6/SCL3/CN64/RE6
PMD7/SDA3/CN65/RE7
PMA5/RP21/C1IND/CN8/RG6
RP26/PMA4/C1INC/CN9/RG7
PMA3/RP19/C2IND/CN10/RG8
MCLR
RP27/PMA2/C2INC/CN11/RG9
VSS
VDD
PGEC3/RP18/VBUSON/C1INA/AN5/CN7/RB5
PGED3/RP28/USBOEN/C1INB/AN4/CN6/RB4
VPIO/C2INA/AN3/CN5/RB3
VMIO/RP13/C2INB/AN2/CN4/RB2
PGEC1/RP1/VREF-/AN1/CN3/RB1
PGED1/RP0/PMA6/VREF+/AN0/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC24FJXXXGB106
48
RPI37/SOSCO/C3INC/TICK/
CN0/RC14
47 SOSCI/C3IND/CN1/RC13
46 RP11/DMH/CN49/INT0/RD0
45 RP12/PMCS1/CN56/RD11
44 RP3/SCL1/PMCS2/CN55/RD10
43 RP4/DPLN/SDA1/CN54/RD9
42 RP2/DMLN/RTCC/CN53/RD8
41 VSS
40 OSCO/CLKO/CN22/RC15
39 OSCI/CLKI/CN23/RC12
38 VDD
37 D+/RG2
36 D-/RG3
35 VUSB
34 VBUS
33 RP16/USBID/CN71/RF3
www.DataSheet4U.com
Legend:
RPn represents remappable pins for Peripheral Pin Select feature.
© 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 3
5 Page 
PIC24FJ256GB110 FAMILY
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC24FJ64GB106
• PIC24FJ128GB106
• PIC24FJ192GB106
• PIC24FJ256GB106
• PIC24FJ64GB108
• PIC24FJ128GB108
• PIC24FJ192GB108
• PIC24FJ256GB108
• PIC24FJ64GB110
• PIC24FJ128GB110
• PIC24FJ192GB110
• PIC24FJ256GB110
This expands on the existing line of Microchip‘s 16-bit
microcontrollers, combining an expanded peripheral
feature set and enhanced computational performance
with a new connectivity option: USB On-The-Go. The
PIC24FJ256GB110 family provides a new platform for
high-performance USB applications which may need
more than an 8-bit platform, but don’t require the power
of a digital signal processor.
1.1 Core Features
1.1.1 16-BIT ARCHITECTURE
Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC® digital signal controllers. The PIC24F CPU core
offers a wide range of enhancements, such as:
• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces
• Linear addressing of up to 12 Mbytes (program
space) and 64 Kbytes (data)
• A 16-element working register array with built-in
software stack support
• A 17 x 17 hardware multiplier with support for
integer math
• Hardware support for 32 by 16-bit division
• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages such as ‘C’
• Operational performance up to 16 MIPS
1.1.2 POWER-SAVING TECHNOLOGY
All of the devices in the PIC24FJ256GB110 family
incorporate a range of features that can significantly
reduce power consumption during operation. Key
items include:
www.DataSh•eeOt4nU-t.choem-Fly Clock Switching: The device clock
can be changed under software control to the
Timer1 source or the internal, low-power RC
oscillator during operation, allowing the user to
incorporate power-saving ideas into their software
designs.
• Doze Mode Operation: When timing-sensitive
applications, such as serial communications,
require the uninterrupted operation of peripherals,
the CPU clock speed can be selectively reduced,
allowing incremental power savings without
missing a beat.
• Instruction-Based Power-Saving Modes: The
microcontroller can suspend all operations, or
selectively shut down its core while leaving its
peripherals active, with a single instruction in
software.
1.1.3
OSCILLATOR OPTIONS AND
FEATURES
All of the devices in the PIC24FJ256GB110 family offer
five different oscillator options, allowing users a range
of choices in developing application hardware. These
include:
• Two Crystal modes using crystals or ceramic
resonators.
• Two External Clock modes offering the option of a
divide-by-2 clock output.
• A Fast Internal Oscillator (FRC) with a nominal
8 MHz output, which can also be divided under
software control to provide clock speeds as low as
31 kHz.
• A Phase Lock Loop (PLL) frequency multiplier,
available to the external oscillator modes and the
FRC oscillator, which allows clock speeds of up to
32 MHz.
• A separate internal RC oscillator (LPRC) with a
fixed 31 kHz output, which provides a low-power
option for timing-insensitive applications.
The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor. This
option constantly monitors the main clock source
against a reference signal provided by the internal
oscillator and enables the controller to switch to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
1.1.4 EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve. The
consistent pinout scheme used throughout the entire
family also aids in migrating from one device to the next
larger, or even in jumping from 64-pin to 100-pin
devices.
The PIC24F family is pin-compatible with devices in the
dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30. This extends
the ability of applications to grow from the relatively
simple, to the powerful and complex, yet still selecting
a Microchip device.
© 2008 Microchip Technology Inc.
Preliminary
DS39897B-page 9
11 Page | ||
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| PDF Descargar | [ Datasheet PIC24FJ64GB110.PDF ] | |
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