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PDF ICS93732 Data sheet ( Hoja de datos )
| Número de pieza | ICS93732 | |
| Descripción | Low Cost DDR Phase Lock Loop Zero Delay Buffer | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS93732 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS9373 2
Low Cost DDR Phase Lock Loop Zero Delay Buffer
Recommended Application:
DDR Zero Delay Clock Buffer
Product Description/Features:
• Low skew, low jitter PLL clock driver
• Max frequency supported = 266MHz (DDR 533)
• I2C for functional and output control
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• 3.3V tolerant CLK_INT input
Switching Characteristics:
• CYCLE - CYCLE jitter (66MHz): <120ps
• CYCLE - CYCLE jitter (>100MHz): <65ps
• CYCLE - CYCLE jitter (>200MHz): <75ps
• OUTPUT - OUTPUT skew: <100ps
• DUTY CYCLE: 49.5% - 50.5%
Pin Configuration
DDRC0 1
DDRT0 2
VDD 3
DDRT1 4
DDRC1 5
GND 6
SCLK 7
CLK_INT 8
N/C 9
VDDA 10
GND 11
VDD 12
DDRT2 13
DDRC2 14
28 GND
27 DDRC5
26 DDRT5
25 DDRC4
24 DDRT4
23 VDD
22 SDATA
21 N/C
20 FB_INT
19 FB_OUT
18 N/C
17 DDRT3
16 DDRC3
15 GND
28-Pin 209mil SSOP
28-Pin 173mil TSSOP
Block Diagram
SCLK
SDATA
Control
Logic
FB_INT
CLK_INT
PLL
FB_OUTT
DDRT0
DDRC0
DDRT1
DDRC1
DDRT2
DDRC2
DDRT3
DDRC3
DDRT4
DDRC4
DDRT5
DDRC5
Functionality
INPUTS
OUTPUTS
PLL State
AVDD CLK_INT CLKT CLKC FB_OUTT
2.5V
(nom)
L
LH
L
on
2.5V
(nom)
H
HL
H
on
0578H—02/19/04
1 page  
ICS9373 2
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D4(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 6
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D5 (H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
ICS (Slave/Receiver)
D4(H)
Dummy Command Code
Dummy Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Stop Bit
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
How to Read:
Controller (Host)
Start Bit
Address
ICS (Slave/Receiver)
D5(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
ACK
Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches
for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
0578H—02/19/04
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet ICS93732.PDF ] | |
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