PDF PRD1366 Data sheet ( Hoja de datos )

Número de pieza	PRD1366
Descripción	FPGA Power Module
Fabricantes	Analog Devices
Logotipo
Hay una vista previa y un enlace de descarga de PRD1366 (archivo pdf) en la parte inferior de esta página. Total 27 Páginas
No Preview Available ! Reference Design FPGA Power Module 12V input, 8 Outputs at 2A to 8A PRD1366 FEATURES Low cost Meet’s Specification for AVNET Mini Module Plus for Xilinx 7 series Kintex FPGA Hard wired turn on sequence High Efficiency (>93% at full load) 12 V input +/-10% Eight regulated outputs (4 dual output ADP1850 devices) 3.3 V @ 8 A output, 2% tolerance (<5% required) 2.5 V @ 8 A output, 2% tolerance (<5% required) 2.0 V @ 2 A output, 2% tolerance (<3% required) 1.8 V @ 6 A output, 2% tolerance (<5% required) 1.5 V/1.35 V @ 4 A jumper selectable output, 2% (<5% required) 1.2 V @ 4 A output, 2% tolerance (<2.5% required) 1.0 V @ 6 A output, 2% tolerance (<3% required) Second 1.0 V @ 6 A output, 2% tolerance (<3% required) DESCRIPTION The Analog Devices Power Module provides a proven robust design for powering Xilinx 7 series devices. Designed to meet the tolerance and sequencing guidelines set forth by Xilinx, the Analog Devices Power Module provides a highly optimized controller based design utilizing the ADP1850 dual output synchronous buck controller. This design uses four dual channel ADP1850 controllers to achieve 8 independent outputs. It utilizes an innovative clocking scheme deriving the clock signal from the switchnodes of the first rails to power up. This reduces channel interaction and beat frequencies that would be present without synchronization and eliminates a costly external clock source. It meets recommended start up sequencing for Xilinx 7 series devices: Vccint -> Vccaux -> Vccaux_io -> Vcco Table 1. Measured results Spec Total Loss (Iout =max all rails) Power delived Vout ripple Value 6.0 84 10 Units W W mVppk on each rail Rev. 2 Reference designs are as supplied “as is” and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. No license is granted by implication or otherwise under any patents or other intellectual property by application or use of reference designs. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Analog Devices reserves the right to change devices or specifications at any time without notice. Trademarks and registered trademarks are the property of their respective owners. Reference designs are not authorized to be used in life support devices or systems. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved. 1 page Reference Design PRD1366 TABLE OF CONTENTS Features ......................................................................................................................................................................1 Description .................................................................................................................................................................1 Revision History.........................................................................................................................................................5 Bill of Materials........................................................................................................................................................10 Layout.......................................................................................................................................................................17 Measurements...........................................................................................................................................................19 TABLE OF FIGURES Figure 1. Schematic page1 1v2@4A, 2v5@8A ....................................................................................................6 Figure 2. Schematic page2 1v8@6A, 1v5@4A ....................................................................................................7 Figure 3. Schematic page3 1v0@6A, 1v0@6A ....................................................................................................8 Figure 4. Schematic page4 3v3@8A, 2v0@2A ....................................................................................................9 Figure 5. Top Layer Layout.................................................................................................................................17 Figure 6. Bottom Layer Layout...........................................................................................................................18 Figure 7. Measured Efficiency over Load...........................................................................................................19 Figure 8. Load Regulation...................................................................................................................................19 Figure 9. Turn on 50Ohm load: Ch1=1V0, Ch2=1V0Mgt, Ch3=1V2, Ch4=2V5 ..............................................20 Figure 10. Turn on 50Ohm load: Ch1=1V5,Ch2=1V8,Ch3=2V0,Ch4=3V3........................................................20 Figure 11. Turn off 50Ohm load: Ch1=1V0, Ch2=1V0Mgt, Ch3=1V2, Ch4=2V5..............................................21 Figure 12. Turn off 50Ohm load: Ch1=1V5,Ch2=1V8,Ch3=2V0,Ch4=3V3 .......................................................21 Figure 13. Ripple No load: Ch1=1V0, Ch2=1V0Mgt, Ch3=1V2, Ch4=2V5 .......................................................22 Figure 14. Ripple No load: Ch1=1V5,Ch2=1V8,Ch3=2V0,Ch4=3V3.................................................................22 Figure 15. Ripple half load: Ch1=1V0, Ch2=1V0Mgt, Ch3=1V2, Ch4=2V5......................................................23 Figure 16. Ripple half load: Ch1=1V5,Ch2=1V8,Ch3=2V0,Ch4=3V3 ...............................................................23 Figure 17. Ripple full load: Ch1=1V0, Ch2=1V0Mgt, Ch3=1V2, Ch4=2V5.......................................................24 Figure 18. Ripple full load: Ch1=1V5,Ch2=1V8,Ch3=2V0,Ch4=3V3 ................................................................24 Figure 19. Load release 100% to 50% load: Ch1=1V0, Ch2=1V0Mgt, Ch3=1V2, Ch4=2V5.............................25 Figure 20. Load release 100% to 50% load: Ch1=1V5,Ch2=1V8,Ch3=2V0,Ch4=3V3 ......................................25 Figure 21. Load step 50% to 100% load: Ch1=1V0, Ch2=1V0Mgt, Ch3=1V2, Ch4=2V5 .................................26 Figure 22. Load step 50% to 100% load: Ch1=1V5,Ch2=1V8,Ch3=2V0,Ch4=3V3 ...........................................26 REVISION HISTORY 11/18/2011—Revision 0: Initial Version r0 board 1/27/2012—Revision 1: Update Schematic and BOM for r1 board Rev. 2 \| Page 5 of 27 5 Page Reference Design PRD1366 Des 2Rf1 2Rf2 2Ren1 2Rsn 2Csn 2Cls 2Cbst 2Clim 2Css 2Cc1 2Cc0 2Cfb 2Cff 1Cvin 1Cvcc0 1Cgnd 1Rdr 1Cdr 1Rfreq 1Rvin 1Rrsgnd 1RLsgnd Cin2 Lin Cin3 Rin U2 3L1 3QH1 3QL1 3Co0…3Co2 3Co3…3Co4 3Cin1 3Rr 3Rcgs 3Rlim1 3Rc 3Rrs 3RLs 3Rf3 3Rf1 3Rf2 3Ren1 3Ren2 3Ren3 3Rclk MFG Vishay Vishay Vishay Murata Murata Murata Murata Murata Murata Murata Murata Murata Murata Vishay Murata Vishay Vishay Vishay Vishay Nichicon Cooper Taiyo ADI Coilcraft Bourns Infineon Infineon Murata Murata Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Part Number 1% Metal Film 1% Metal Film 1% Metal Film No Pop No Pop No Pop X5R or X7R 10% NPO or COG 10% NPO or COG 10% NPO or COG 10% NPO or COG X5R or X7R 10% NPO or COG X5R or X7R X5R or X7R X5R or X7R 1% Metal Film X5R or X7R 1% Metal Film 5% Metal Film Zero Ohm Jumper 5% Metal Film PCV1D271MCL1GS FP1007R1-R30-R EMK212 BJ106KG-T No Pop ADP1850ACPZ SER1052-222MLB SRP1055-2R2M BSZ060NE2LS BSZ0902NS GRM32ER60J107M No Pop GRM32DR71C106K 1% Metal Film No Pop 1% Metal Film 1% Metal Film 5% Metal Film 1% Metal Film 1% Metal Film 1% Metal Film 1% Metal Film No Pop No Pop 1% Metal Film No Pop Component Specs 93.1KΩ 29.4KΩ 10.0KΩ 100nF, >6v 18pF, >20v 56nF, >6v 150pF, >6v 3.3pF, >6v 100nF>6v 220pF 1uF, 25v 1uF, 6.3v 1uF, 6.3v 10Ω 1uF, 6.3v 165KΩ 1.0Ω 0Ω 1.0Ω 270uF, 20V, Poly 300nH ,0.29mΩ 10uF, 16V, X5R Controller 2.2uH,6mΩ 2.2uH,5.8mΩ 8.1mΩ, 25V 3.5mΩ, 30V 100uF, 6.3V, X5R 10uF, 16V, X7R 100KΩ 866Ω 191KΩ 1.0Ω 100Ω 1.82KΩ 46.4KΩ 23.2KΩ 10.0KΩ Pkg 0402 0402 0402 0805 0402 0402 0402 0402 0402 0402 0402 0402 0402 0603 0603 0603 0805 0603 0402 0402 0402 0402 10mm 8 x 10 0805 0805 LFCSP32 12 x 11 11.3x9.4 PP8-3x3 PP8-3x3 1210 1210 1210 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 Qty Area Hgt (mm^2) (mm) 1 0.5 0.5 1 0.5 0.5 1 0.5 0.5 0 0.0 0.0 0 0.0 0.0 0 0.0 0.0 1 0.5 0.5 1 0.5 0.5 1 0.5 0.5 1 0.5 0.5 1 0.5 0.5 1 0.5 0.5 1 0.5 0.5 1 3.1 0.5 1 3.1 0.5 1 3.1 0.5 1 3.1 0.5 1 3.1 0.5 1 0.5 0.5 1 0.5 0.5 1 0.5 0.5 1 0.5 0.5 1 100.0 10.0 1 83.2 7.0 1 2.5 1.3 0 0.0 0.0 1 26.0 1.0 1 117.0 5.2 1 11.6 1 11.6 3 24.0 0 0.0 1 8.0 1 0.5 0 0.0 1 0.5 1 0.5 1 0.5 1 0.5 1 0.5 1 0.5 1 0.5 0 0.0 0 0.0 1 0.5 0 0.0 1.1 1.1 2.0 0.0 2.0 0.5 0.0 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.0 0.0 0.5 0.0 Rev. 2 \| Page 11 of 27 11 Page

Páginas	Total 27 Páginas
PDF Descargar	[ Datasheet PRD1366.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
PRD1366	FPGA Power Module	Analog Devices

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar