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PDF NVP1114A Data sheet ( Hoja de datos )
| Número de pieza | NVP1114A | |
| Descripción | 4-Ch Video Decoder | |
| Fabricantes | Nextchip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de NVP1114A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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NVP1114A
4-Ch Video Decoder with 4-Ch Audio Codec,
Video Encoder.
Information contained here is subject to change without notice.
Make sure to check and use an updated version of the Data sheet.
www.nextchip.com
2009.08.01.
REV 1.0
1 page  
NVP1114A
4-Ch Video Decoder with 4-Ch Audio Codec, Video Encoder
5. I2C Wire Interface ····································································································································································· 37
5.1. Bank Operation ·································································································································································· 37
6. Register Description ································································································································································· 38
7. Electrical characteristics ························································································································································ 81
7.1 Absolute Maximum Ratings ············································································································································· 81
7.2 Recommended Operating Condition ···························································································································· 81
7.3 DC Characteristics ····························································································································································· 81
7.4 AC Characteristics ····························································································································································· 82
8. System Application ··································································································································································· 82
8.1 Recommended Register ················································································································································· 82
8.1.1 Order for NTSC Recommended Register Setting ······················································································· 83
8.1.2 Order for PAL Recommended Register Setting ······························································································· 85
8.2 Index of System Application ········································································································································ 87
8.3 4 Channel, Master Mode ··············································································································································· 89
8.3.1 Block Diagram (4 Channel, I2S Master Mode) ····························································································· 89
8.3.2 Circuit Configuration (4 Channel, I2S Master Mode) ·················································································· 90
8.4 4 Channel, Slave Mode ················································································································································· 91
8.4.1 Block Diagram (4 Channel, I2S Slave Mode) ································································································ 91
8.4.2 Circuit Configuration (4 Channel, I2S Slave Mode) ····················································································· 92
8.5 8 Channel, Master Mode ··············································································································································· 93
8.5.1 Block Diagram ·························································································································································· 93
8.5.2 Circuit Configuration ··············································································································································· 95
8.6 8 Channel, Slave Mode ················································································································································· 97
8.6.1 Block Diagram ·························································································································································· 97
8.6.2 Circuit Configuration ··············································································································································· 99
8.7 16 Channel, Master Mode ·········································································································································· 101
8.7.1 Block Diagram ························································································································································ 101
8.7.2 Circuit Configuration ············································································································································ 103
8.8 16 Channel, Slave Mode ············································································································································· 107
8.8.1 Block Diagram ························································································································································ 107
8.8.2 Circuit Configuration ············································································································································ 109
8.9 Register Setting ······························································································································································ 113
8.9.1 16 Channel, 16bit@16KHz, I2S Master/Slave Mode (NVP1114A Only) ··············································· 113
8.9.2 16 Channel, 8bit@16KHz, I2S Master/Slave Mode (NVP1114A Only) ················································· 114
8.9.3 16 Channel, 16bit@8KHz, I2S Master/Slave Mode (NVP1114 Only) ··················································· 115
8.9.4 16 Channel, 8bit@8KHz, I2S Master/Slave Mode (NVP1114A Only) ··················································· 116
8.9.5 16 Channel, 16bit@16KHz, I2S Master/Slave Mode (NVP1114A + NVP1104A) ······························· 117
8.9.6 16 Channel, 8bit@16KHz, I2S Master/Slave Mode (NVP1114A + NVP1104A) ································· 118
8.9.7 16 Channel, 16bit@8KHz, I2S Master/Slave Mode (NVP1114A + NVP1104A) ································· 119
8.9.8 16 Channel, 8bit@8KHz, I2S Master/Slave Mode (NVP1114A + NVP1104A) ··································· 120
8.10 Package Information ··················································································································································· 121
9. Revision History ··································································································································································· 122
10. Contact Information ····························································································································································· 122
2009.08.01. (REV 1.0)
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5 Page 
NVP1114A
4-Ch Video Decoder with 4-Ch Audio Codec, Video Encoder
NVP1114A provides the peaking filter and Gain control for emphasizing or depressing the high-frequency
area to avoid this problem. The luma filter is applied to this purpose and its characteristics can be
controlled by register (Y_FIR_MODE, BANK0, 0x28/38/48/58[3:2]) via I2C interface.
Figure 2.4. Peaking Filter Characteristic
2.7. Chroma Processing
: Chroma processing mainly consists of 3 parts: demodulation, filtering, and ACC(Automatic Chroma-gain
Control). The chroma demodulator receives modulated chroma from YC separator, and generates demodulated
color difference data. Demodulated data must be low-pass filtered to reduce anti-aliasing artifacts. Figure
2.5. shows chroma demodulation and filtering process. Chroma LPF frequency characteristics is demonstrated
in Figure 2.6. Users can select the chroma filter through I2C interface (CLPF_SEL, BANK0, 0x7C[1:0]).
2009.08.01. (REV 1.0)
Figure 2.5. Chroma Process
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| PDF Descargar | [ Datasheet NVP1114A.PDF ] | |
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