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PDF NL204153BM21-05 Data sheet ( Hoja de datos )
| Número de pieza | NL204153BM21-05 | |
| Descripción | TFT MONOCHROME LCD MODULE | |
| Fabricantes | NEC | |
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TFT MONOCHROME LCD MODULE
NL204153BM21-05
54cm (21.3 Type)
QXGA
PRELIMINARY DATA SHEET
DOD-PD-0418 (6th edition)
This PRELIMINARY DATA SHEET is updated
document from DOD-PD-0246(5).
All information is subject to change without notice.
Please confirm the sales representative before
starting to design your system.
Document Number: DOD-PD-0418 (6th edition) 1 ã NEC LCD Technologies, Ltd.
Published date: March 2004 CP(N)
2003, 2004 All rights reserved.
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NL204153BM21-05
2. GENERAL SPECIFICATIONS
Display area
Diagonal size of display
Drive system
Display grayscale
Pixel
Pixel arrangement
Dot pitch
Pixel pitch
Module size
Weight
Contrast ratio
Viewing angle
433.152 (H) × 324.864 (V) mm (typ.)
54 cm (21.3 inches)
a-Si TFT active matrix
256 gray scale per 1 dot (8-bit)
(1 pixel consists of 3 dots (766 gray scale).)
2,048 (H) × 1,536 (V) pixels
Sub-pixel vertical stripe
0.0705 (H) × 0.2115 (V) mm
0.2115 (H) × 0.2115 (V) mm
457.0 (W) × 350.0 (H) × 25.0 (D) mm (typ.)
3,800 g (typ.)
700:1 (typ.)
At the contrast ratio ≥ 10:1
• Horizontal: Right side 85° (typ.), Left side 85° (typ.)
• Vertical: Up side 85° (typ.), Down side 85° (typ.)
6
Designed viewing direction
Polarizer surface
Polarizer pencil-hardness
Response time
Luminance
Signal system
Viewing angle with optimum grayscale (γ=DICOM): normal axis
6
Antiglare
2H (min.) [by JIS K5400]
Ton+Toff (10%←→ 90%)
(35) ms (typ.)
At IBL= 6.0mArms / lamp
800 cd/m2 (typ.)
4 ports LVDS interface (THC63LVD824×2 pcs, THine Electronics, Inc.
or equivalent)
LCR 8-bit signals, Data enable signal (DE), Dot clock (CLK)
6
Power supply voltage
LCD panel signal processing board: 12.0V
Backlight
Power consumption
Edge light type: 6 cold cathode fluorescent lamps (without inverter)
At checkered flag pattern and IBL= 6.0mArms / lamp
34.2 W (typ.)
PRELIMINARY DATA SHEET DOD-PD-0418 (6th edition)
5
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NL204153BM21-05
4.4 POWER SUPPLY VOLTAGE SEQUENCE
VDD
Note1, Note2
VDD ON
10.8V
0V
5ms < Tr < 80ms
VDD OFF
9.6V 10.8V
VDD dip < 20ms
LVDS Signals *1,*2
Note3
0V
CS, SCLK, SDAT
Note3
VALID period
t≥20ms Note4
VALID period
10.8V
Toff > 200ms
10ms < t < 35ms
0ms < t < 35ms
*1: DA0+/-, DA1+/-, DA2+/-, DA3+/-, CKA+/-, DB0+/-, DB1+/-, DB2+/-, DB3+/-, CKB+/-,
DC0+/-, DC1+/-, DC2+/-, DC3+/-, CKC+/-, DD0+/-, DD1+/-, DD2+/-, DD3+/-, CKD+/-
*2: LVDS signals should be measured at the terminal of 100Ω resistor.
Note1: In terms of voltage variation (voltage drop) while VDD rising edge is below 10.8V, a
protection circuit may work, and then this product may not work.
Note2: VDD should be 10.8V or more during VDD ON period.
Note3: LVDS signals and CS, SCLK, SDAT must be Low or High-impedance, exclude the
VALID period (See above sequence diagram), in order to avoid that internal circuits is
damaged.
If some of signals are cut while this product is working, even if the signal input to it once
again, it might not work normally. If customer stops the display and function signals,
they should be cut VDD.
Note4: At the beginning of the serial communication mode, take 20ms or more after the LVDS
signal input. When writing the LUT data, see “4.7 TEN-bit LOOK UP TABLE FOR
GAMMA ADJUSTMENT”.
Note5: The backlight inverter voltage should be inputted within the valid period of LVDS signals,
in order to avoid unstable data display.
PRELIMINARY DATA SHEET DOD-PD-0418 (6th edition)
11
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