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PDF NCP1081 Data sheet ( Hoja de datos )
| Número de pieza | NCP1081 | |
| Descripción | Integrated High Power PoE-PD Interface & DC-DC Converter Controller | |
| Fabricantes | ON Semiconductor | |
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NCP1081
Integrated High Power
PoE-PD Interface & DC-DC
Converter Controller
Introduction
The NCP1081 is a member of ON Semiconductor’s high power
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HIPO Power over Ethernet Powered Device (PoE−PD) product family
and represents a robust, flexible and highly integrated solution
targeting demanding medium and high power Ethernet applications. It
combines in a single unit an enhanced PoE−PD interface supporting
the IEEE802.3af and the 802.3at standard and a flexible and
1
configurable DC−DC converter controller.
The NCP1081’s exceptional capabilities offer new opportunities for
the design of products powered directly over Ethernet lines,
TSSOP−20 EP
DE SUFFIX
CASE 948AB
eliminating the need for local power adaptors or power supplies and
drastically reducing the overall installation and maintenance cost.
ON Semiconductor’s unique manufacturing process and design
enhancements allow the NCP1081 to deliver up to 25.5 W for the
IEEE802.3at standard and up to 40 W for proprietary high power PoE
applications. The NCP1081 enables the IEEE802.3at and implements
a two event physical layer classification. Additional proprietary
classification procedures support high power power sourcing
equipment (PSE) on the market. The unique high power features
leverage the significant cost advantages of PoE− enabled systems to a
much broader spectrum of products in emerging markets such as
industrial ethernet devices, PTZ and Dome IP cameras, RFID readers,
MIMO WLAN access points, high end VoIP phones, notebooks, etc.
The integrated current mode DC−DC controller facilitates isolated
and non−isolated fly−back, forward and buck converter topologies. It
NCP1081 = Specific Device Code
XXXX = Date Code
Y = Assembly Location
ZZ = Traceability Code
has all the features necessary for a flexible, robust and highly efficient
design including programmable switching frequency, duty cycle up to
80 percent, slope compensation, and soft start−up.
The NCP1081 is fabricated in a robust high voltage
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
process and integrates a rugged vertical N−channel DMOS
with a low loss current sense technique suitable for the most
demanding environments and capable of withstanding harsh
environments such as hot swap and cable ESD events.
The NCP1081 complements ON Semiconductor’s ASSP
portfolio in industrial devices and can be combined with
stepper motor drivers, CAN bus drivers and other high−
voltage interfacing devices to offer complete solutions to the
• Extended Power Ranges up to 40 W
• Programmable Classification Current
• Adjustable Under Voltage Lock Out
• Programmable Inrush Current Limit
• Programmable Operational Current Limit up to
1100 mA for Extended Power Ranges
industrial and security market.
• Over−temperature Protection
Features
• These are Pb−Free Devices
Powered Device Interface
• Supporting the IEEE802.3af and the 802.3at Standard
• Supports IEEE802.3at Two Event Layer 1
Classification
• High Power Layer 1 Classification Indicator
• Industrial Temperature Range −40°C to 85°C with Full
Operation up to 150°C Junction Temperature
• 0.6 W Hot−swap Pass−switch with Low Loss Current
Sense Technique
• Vertical N−channel DMOS Pass−switch offers the
Robustness of Discrete MOSFETs with Integrated
Temperature Control
© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 7
1
Publication Order Number:
NCP1081/D
1 page  
NCP1081
Table 1. PIN DESCRIPTIONS
Name
Pin No.
Type
VPORTP 1 Supply
VPORTN1
VPORTN2
6,8
Ground
RTN
7 Ground
ARTN
14 Ground
VDDH
16 Supply
VDDL
17 Supply
CLASS
INRUSH
ILIM1
UVLO
GATE
OSC
nCLASS_AT
COMP
2
4
5
3
15
11
13
18
Input
Input
Input
Input
Output
Input
Output,
Open Drain
I/O
FB
CS
SS
TEST1
TEST2
EP
19 Input
12 Input
20 Input
9 Input
10 Input
Description
Positive input power. Voltage with respect to VPORTN1,2.
Negative input power. Connected to the source of the internal pass−switch.
DC−DC controller power return. Connected to the drain of the internal pass−switch. It must
be connected to ARTN. This pin is also the drain of the internal pass−switch.
DC−DC controller ground pin. Must be connected to RTN as a single point ground connection
for improved noise immunity.
Output of the 9 V LDO internal regulator. Voltage with respect to ARTN. Supplies the internal
gate driver. VDDH must be bypassed to ARTN with a 1 mF or 2.2 mF ceramic capacitor with
low ESR.
Output of the 3.3 V LDO internal regulator. Voltage with respect to ARTN. This pin can be
used to bias an external low−power LED (1 mA max.) connected to nCLASS_AT, and can
also be used to add extra biasing current in the external opto−coupler. VDDL must be by-
passed to ARTN with a 330 nF or 470 nF ceramic capacitor with low ESR.
Classification current programming pin. Connect a resistor between CLASS and VPORTN1,2.
Inrush current limit programming pin. Connect a resistor between INRUSH and VPORTN1,2.
Operational current limit programming pin. Connect a resistor between ILIM1 and
VPORTN1,2.
DC−DC controller under−voltage lockout input. Voltage with respect to VPORTN1,2. Connect
a resistor−divider from VPORTP to UVLO to VPORTN1,2 to set an external UVLO threshold.
DC−DC controller gate driver output pin.
Internal oscillator frequency programming pin. Connect a resistor between OSC and ARTN.
Active−low, open−drain Layer 1 dual−finger classification indicator.
Output of the internal error amplifier of the DC−DC controller. COMP is pulled−up internally to
VDDL with a 5 kW resistor. In isolated applications, COMP is connected to the collector of the
opto−coupler. Voltage with respect to ARTN.
DC−DC controller inverting input of the internal error amplifier. In isolated applications, the pin
should be strapped to ARTN to disable the internal error amplifier.
Current−sense input for the DC−DC controller. Voltage with respect to ARTN.
Soft−start input for the DC−DC controller. A capacitor between SS and ARTN determines the
soft−start timing.
Digital test pin must always be connected to VPORTN1,2.
Digital test pin must always be connected to VPORTN1,2.
Exposed pad. Connected to VPORTN1,2 ground.
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5
5 Page 
NCP1081
DESCRIPTION OF OPERATION
Powered Device Interface
The PD interface portion of the NCP1081 supports the
IEEE802.3af and 802.3at defined operating modes:
detection signature, current source classification, inrush and
operating current limits. In order to give more flexibility to
the user and also to keep control of the power dissipation in
the NCP1081, both current limits are configurable. The
device enters operation once its programmable Vuvlo_on
threshold is reached, and operation ceases when the supplied
voltage falls below the Vuvlo_off threshold. Sufficient
hysteresis and Uvlo filter time are provided to avoid false
power on/off cycles due to transient voltage drops on the
cable.
Detection
During the detection phase, the incremental equivalent
resistance seen by the PSE through the cable must be in the
IEEE802.3af standard specification range (23.75 kW to
26.25 kW) for a PSE voltage from 2.7 V to 10.1 V. In order
to compensate for the non-linear effect of the diode bridge
and satisfy the specification at low PSE voltage, the
NCP1081 presents a suitable impedance in parallel with the
25.5 kW Rdet external resistor connected between VPORTP
and VPORTN. For some types of diodes (especially Schottky
diodes), it may be necessary to adjust this external resistor.
When the Detection_Off level is detected (typically
11.5 V) on VPORTP, the NCP1081 turns on its internal
3.3 V regulator and biasing circuitry in anticipation of the
classification phase as the next step.
Classification
Once the PSE device has detected the PD device, the
classification process begins. The NCP1081 is fully capable
of responding and completing all classification handshaking
procedures as described next.
Classification Current Source Generation
In classification, the PD regulates a constant current
source that is set by the external resistor RCLASS value on
the CLASS pin. Figure 6 shows the schematic overview of
the classification block. The current source is defined as:
Iclass
+
Vbg
Rclass
,
(where Vbg is 1.2
V)
VPORTP
VDDA1
1.2 V
CLASS
Rclass
VPORTN1,2
NCP1081
Figure 6. Classification Block Diagram
The NCP1081 can handle all defined types of
classification, IEEE802.3af, 802.3at and proprietary
classification.
In the IEEE802.3af standard the classification is
performed with a Single Event Layer 1 classification.
Depending on the current level set during that single event
the power level is determined. The IEEE802.3at standard
allows two ways of classification which can also be
combined. These two approaches enable higher power
applications through a variety of PSE equipment.
For power injectors and midspans a pure physical
hardware handshake is introduced called Two Event Layer 1
classification. This approach allows equipment that has no
data link between PSE and PD to classify as high power.
Since switches can establish a data link between PSE and
PD, a software handshake is possible. This type of
handshake is called Layer 2 classification (or Data Link
Layer classification). It has the main advantage of having a
finer power resolution and the ability for the PSE and PD to
participate in dynamic power allocation.
Table 4. Single and Dual Event Classification
Standard Layer
Handshake
802.3af
1 Single event physical classification
802.3at
1 Two event physical classification
802.3at
2 Data-link (IP) communication
classification
One Event Layer 1 Classification
An IEEE802.3af compliant PSE performs only One Event
Layer 1 classification event by increasing the line voltage
into the classification range only once.
Two Event Layer 1 Classification
A IEEE802.3at compliant PSE using this physical
classification performs two classification events and looks
for the appropriate response from the PD to check if the PD
is IEEE802.3at compatible.
The PSE will generate the sequence described in Figure 7.
During the first classification finger, the PSE will measure
the classification current which should be 40 mA if the PD
is at compliant. If this is the case, the PSE will exit the
classification range and will force the line voltage into the
Mark Event range. Within this range, the PSE may check the
non-valid input signature presented by the PD (using the two
point measurement defined in the IEEE802.3af standard).
Then the PSE will repeat the same sequence with the second
classification finger. A PD which has detected the sequence
“Finger + Mark + Finger + Mark” knows the PSE is
IEEE802.3at compliant, meaning the PSE will deliver more
current on the port. (Note that a PSE IEEE802.3at compliant
may apply more than two fingers, but the final result will be
the same as two fingers).
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11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet NCP1081.PDF ] | |
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