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PDF MIC5842 Data sheet ( Hoja de datos )
| Número de pieza | MIC5842 | |
| Descripción | 8-Bit Serial-Input Latched Drivers | |
| Fabricantes | Micrel Semiconductor | |
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MIC5841/5842
8-Bit Serial-Input Latched Drivers
General Description
Using BiCMOS technology, the MIC5841/5842 integrated
circuits were fabricated to be used in a wide variety of
peripheral power driver applications. The devices each
have an eight-bit CMOS shift register, CMOS control
circuitry, eight CMOS data latches, and eight bipolar
current-sink Darlington output drivers.
These two devices differ only in maximum voltage ratings.
The MIC5842 offers premium performance with a
minimum output breakdown voltage rating of 80V (50V
sustaining). The drivers can be operated with a split supply
where the negative supply is down to –20V.
The 500mA outputs, with integral transient-suppression
diodes, are suitable for use with lamps, relays, solenoids
and other inductive loads.
These devices have improved speed characteristics. With
a 5V logic supply, they will typically operate faster than
5 MHz. With a 12V supply, significantly higher speeds are
obtained. The CMOS inputs are compatible with standard
CMOS, PMOS, and NMOS logic levels. TTL or DTL
circuits may require the use of appropriate pull-up
resistors. By using the serial data output, the drivers can
be cascaded for interface applications requiring additional
drive lines.
The MIC5840 family is available in DIP, PLCC, and SOIC
packages. Because of limitations on package power
dissipation, the simultaneous operation of all drivers at
maximum rated current might require a reduction in duty
cycle. A copper-alloy lead frame provides for maximum
package power dissipation.
Features
• 3.3 MHz Minimum Data-Input Rate
• CMOS, PMOS, NMOS, TTL Compatible
• Internal Pull-Up/Pull-Down Resistors
• Low-Power CMOS Logic and Latches
• High-Voltage Current-Sink Outputs
• Output Transient-Protection Diodes
• Single or Split Supply Operation
Ordering Information
Part Number
Standard
MIC5841BN
MIC5841BV
MIC5841BWM
MIC5842BN
MIC5842BV
MIC5842BWM
Pb-Free
MIC5841YN
MIC5841YV
MIC5841YWM
MIC5842YN
MIC5842YV
MIC5842YWM
Temperature Range
Package
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
18-Pin Plastic DIP
20-Pin PLCC
18-Pin Wide SOIC
18-Pin Plastic DIP
20-Pin PLCC
18-Pin Wide SOIC
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
May 2006
M9999-050506
(408) 955-1690
1 page  
Micrel, Inc.
MIC5841/42
Timing Conditions
(TA = 25°C Logic Levels are VDD and VSS)
VDD = 5V
A. Minimum Data Active Time Before Clock Pulse (Data Set-Up Time)...................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse (Data Hold Time) ............................................................................ 75 ns
C. Minimum Data Pulse Width ................................................................................................................................... 150 ns
D. Minimum Clock Pulse Width................................................................................................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ........................................................................................... 300 ns
F. Minimum Strobe Pulse Width.................................................................................................................................. 100 ns
G. Typical Time Between Strobe Activation and Output Transition............................................................................ 500 ns
SERIAL DATA present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the ENABLE input be high during serial data entry.
When the ENABLE input is high, all of the output buffers are disabled (OFF) without affecting information stored in the
latches or shift register. With the ENABLE input low, the outputs are controlled by the state of the latches.
MIC5840 Family Truth Table
Serial
Data
Input
H
L
X
Clock
Input
Shift Register Contents
I1 I2 I3 … I8
H R1 R2 … R7
L R1 R2 … R7
R1 R2 R3 … R8
X X X…X
P1 P2 P3 … P8
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
Serial
Data
Output
R7
R7
R8
X
P8
Strobe
Input
Latch Contents
I1 I2 I3 … I8
Output
Enable
Output Contents
I1 I2 I3 … I8
L R1 R2 R3 … R8
H P1 P2 P3 … P8 L P1 P2 P3 … P8
X X X … X H H H H …H
May 2006
5 M9999-050506
(408) 955-1690
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MIC5842.PDF ] | |
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