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PDF MAX692 Data sheet ( Hoja de datos )

Número de pieza MAX692
Descripción Microprocessor Supervisory Circuits
Fabricantes Maxim Integrated 
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MAX690–MAX695
Microprocessor Supervisory Circuits
General Description
The MAX690 family of supervisory circuits reduces the
complexity and number of components required for
power supply monitoring and battery control functions in
microprocessor systems. These include µP reset and
backup-battery switchover, watchdog timer, CMOS RAM
write protection, and power-failure warning. The MAX690
family significantly improves system reliability and accu-
racy compared to that obtainable with separate ICs or
discrete components.
The MAX690, MAX692, and MAX694 are supplied in
8-pin packages and provide four functions:
● A reset output during power-up, power-down, and
brownout conditions.
● Battery backup switching for CMOS RAM, CMOS
microprocessor or other low power logic.
● A Reset pulse if the optional watchdog timer has not
been toggled within a specified time.
● A 1.3V threshold detector for power fail warning, low
battery detection, or to monitor a power supply other
than +5V.
The MAX691, MAX693, and MAX695 are supplied in 16-pin
packages and perform all MAX690, MAX692, MAX694
functions, plus:
● Write protection of CMOS RAM or EEPROM.
● Adjustable reset and watchdog timeout periods.
● Separate outputs for indicating a watchdog timeout,
backup-battery switchover, and low VCC.
Typical Operating Circuit
+5V
VCC
VOUT
POWER TO
µP
VBATT
CMOS RAM POWER
MAX690
µP
SYSTEM
PFI RESET
PFO
WDI
GND
µP RESET
µP NMI
I/O
LINE
MAX690 TYPICAL APPLICATION
Benefits and Features
● Supervisory Function Integration Saves Board Space
while Fully Protecting Microprocessor-Based Systems
• Precision Voltage Monitor
-- 4.65V (MAX690, MAX691, MAX694, MAX695)
-- 4.40V (MAX692, MAX693)
• Power OK/Reset Time Delay
-- 50ms, 200ms, or Adjustable
• Watchdog Timer
-- 100ms, 1.6s, or Adjustable
• Battery Backup Power Switching
• Voltage Monitor for Power Fail or Low Battery
Warning
• Minimum External Component Count
● Low Power Consumption in Battery Backup Mode
Extends Battery Life
• 1µA Standby Current
● Onboard Gating of Chip Enable Signals Protects
Against Erroneous Data Written to RAM During Low
VCC Events
Applications
● Computers
● Controllers
● Intelligent Instruments
● Automotive Systems
● Critical µP Power Monitoring
Ordering information appears at end of data sheet.
Pin Configurations
TOP VIEW
VOUT 1
VCC 2
GND 3
PFI 4
MAX690
MAX692
MAX694
8 VBATT
7 RESET
6 WDI
5 PFO
VBATT 1
VOUT 2
VCC 3
GND 4
BATT ON 5
LOW LINE 6
OSC IN 7
OSC SEL 8
MAX691
MAX693
MAX695
16 RESET
15 RESET
14 WDO
13 CE IN
12 CE OUT
11 WDI
10 PFO
9 PFI
19-0218; Rev 5; 4/15

1 page




MAX692 pdf
MAX690–MAX695
Microprocessor Supervisory Circuits
Pin Description (continued)
PIN
MAX690/
MAX692/
MAX694
MAX691/
MAX693/
MAX695
5 10
— 13
— 12
NAME
FUNCTION
PFO
CE IN
CE OUT
Output of the Power-Fail Comparator. It goes low when PFI is less than 1.3V. The
comparator is turned off and PFO goes low when VCC is below VBATT.
CE Gating Circuit Input. Connect to GND or VOUT if not used.
CE OUT goes low only when CE IN is low and VCC is above the reset threshold (4.65V
for MAX691 and MAX695, 4.4V for MAX693). See Figure 6.
BATT ON goes high when VOUT is internally switched to the VBATT input. It goes low
5
BATT ON
when VOUT is internally switched to VCC. The output typically sinks 25mA and can
directly drive the base of an external PNP transistor to increase the output current
above the 50mA rating of VOUT.
6
LOW LINE
LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon
as VCC rises above the reset threshold. See Figure 6, Reset Timing.
— 16 RESET Active-High Output. It is the inverse of RESET.
When OSC SEL is unconnected or driven high, the internal oscillator sets the reset time
— 8 OSC SEL delay and watchdog timeout period. When OSC SEL is low, the external oscillator input,
OSC IN, is enabled. OSC SEL has a 3µA internal pullup. See Table 1.
When OSC SEL is low, OSC IN can be driven by an external clock to adjust both the
7
OSC IN
reset delay and the watchdog timeout period. The timing can also be adjusted by
connecting and external oscillator to this pin. See Figure 8. When OSC SEL is high or
floating, OSC IN selects between fast and slow Watchdog timeout periods.
The Watchdog Output (WDO). WDO goes low if WDI remains either high or low for
14
WDO
longer than the watchdog timeout period. WDO is set high by the next transition at WDI.
If WDI is unconnected or at mid-supply, WDO remains high. WDO also goes high when
LOW LINE goes low.
www.maximintegrated.com
Maxim Integrated 5

5 Page





MAX692 arduino
MAX690–MAX695
Microprocessor Supervisory Circuits
1.3V Comparator and Power-Fail Warning
The power-fail input (PFI) is compared to an internal
1.3V reference. The power-fail output (PFO) goes low
when the voltage at PFI is less than 1.3V. Typically, PFI is
driven by an external voltage divider which senses either
the unregulated DC input to the system’s 5V regulator or
the regulated 5V output. The voltage divider ratio can be
chosen such that the voltage at PFI falls below 1.3V sev-
eral milliseconds before the +5V supply falls below 4.75V.
PFO is normally used to interrupt the microprocessor so
that data can be stored in RAM before VCC falls below
4.75V and the RESET output goes low (4.5V for MAX692/
MAX693).
The power-fail detector can also monitor the backup bat-
tery to warn of a low battery condition. To conserve bat-
tery power, the power-fail detector comparator is turned
off and PFO is forced when VCC is lower than VBATT
input voltage.
Watchdog Timer and Oscillator
The watchdog circuit monitors the activity of the micro-
processor. If the microprocessor does not toggle the
Watchdog Input (WDI) within the selected timeout period,
a 50ms* RESET pulse is generated. Since many systems
cannot service the watchdog timer immediately after a
reset, the MAX691/MAX693/MAX695 has a longer time-
out period after reset is issued. The normal timeout period
becomes effective following the first transition of WDI after
RESET has gone high. The watchdog timer is restarted
at the end of reset, whether the reset was caused by
lack of activity on WDI or by VCC falling below the reset
threshold. If WDI remains either high or low, reset pulses
will be issued every 1.6s. The watchdog monitor can be
deactivated by floating the watchdog input (WDI).
The watchdog output (WDO, MAX691/MAX693/MAX695
only) goes low if the watchdog timer times out and
remains low until set high by the next transition on the
watchdog input. WDO is also set high when VCC goes
below the reset threshold.
The watchdog timeout period is fixed at 1.6s and the
reset pulse width is fixed at 50ms* on the 8-pin MAX690/
MAX692/MAX694. The MAX691/MAX693/MAX695 allow
these times to be adjusted per Table 1. Figures 8 shows
various oscillator configurations.
The internal oscillator is enabled when OSC SEL is
floating. In this mode, OSC IN selects between the
1.6s and 100ms watchdog timeout periods. In either
case, immediately after a reset the timeout period 1.6s.
This gives the microprocessors time to reintialize the
system. If OSC IN is low, then the 100ms watchdog
period becomes effective after the first transition of WDI.
The software should be written such that the I/O port
driving WDI is left in its power-up reset state until the ini-
tialization routines are completed and the microprocessor
is able to toggle WDI at the minimum watchdog timeout
period of 70ms.
*200ms for MAX694
WATCHDOG INPUT
VCC 2.7V
+
-
-
+
1.0V
TRANSACTION
DETECTOR
FOR EACH TRANSITION
LOW LINE
(HI IF VCC < 4.65V)
HI IF WATCHDOG
INPUT IS FLOATING
PRESCALER
10.24 kHz FROM INTERNAL OSCILLATOR
OR EXTERNALLY SET FREQUENCY FROM
Q6 OSC IN PIN
WATCHDOG TIMEOUT SELECT
RESET
COUNTER
R Q10/12
WATCHDOG
COUNTER
Q11
Q13
R Q15
WATCHDOG
TIMEOUT
SELECTOR
LOGIC
GOES HIGH AT THE
END OF WATCHDOG
TIMEOUT PERIOD
SR
RESET
FLIP FLOP
QQ
SQ
LONG/SHORT
FF
R
LOW
LINE
RS
WATCHDOG
FAULT FF
Q
Figure 7. Watchdog Timer Block Diagram
RESET RESET
WATCHDOG OUTPUT
www.maximintegrated.com
Maxim Integrated 11

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