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PDF RT9212 Data sheet ( Hoja de datos )
| Número de pieza | RT9212 | |
| Descripción | Dual 5V Synchronous Buck PWM DC-DC and Linear Power Controller | |
| Fabricantes | RichTek | |
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Preliminary
RT9212
Dual 5V Synchronous Buck PWM DC-DC
and Linear Power Controller
General Description
The RT9212 is a 3-in-one power controller delivers high
efficiency and tight regulation from two voltage regulating
synchronous buck PWM DC-DC and one linear power
controllers.
The RT9212 can control two independent output voltages
adjustment in range of 0.8V to 4.0V with 180 degrees
channel to channel phase operation to reduce input ripple.
In dual power supply application the RT9212 monitors the
output voltage of both Channel 1 and Channel 2. An
independent PGOOD (power good) signal is asserted for
each channel after the soft-start sequence has completed,
and the output voltage is within ±15% of the set point. The
linear controller drives an external transistor to provide an
adjustable output voltage.
Built-in over-voltage protection prevents the output from
going above 137.5% of the set point by holding the lower
MOSFET on and the upper MOSFET off. Adjustable over-
current protection (OCP) monitors the voltage drop across
the RDS(ON) of the upper MOSFET for each synchronous
buck PWM DC-DC controller individually.
Ordering Information
RT9212
Package Type
C : TSSOP-24
Operating Temperature Range
C : Commercial Standard
P : Pb Free with Commercial Standard
Note :
RichTek Pb-free products are :
−RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
−Suitable for use in SnPb or Pb-free soldering processes.
−100% matte tin (Sn) plating.
Features
z Operating with Single 5V Supply Voltage
z Drives All Low Cost N-Channel MOSFETs
z Voltage Mode PWM Control
z 300kHz Fixed Frequency Oscillator
z Fast Transient Response :
Full 0% to 100% Duty Ratio
z Internal Soft-Start
z Adaptive Non-Overlapping Gate Driver
z Over-Current Fault Monitor on VCC, No Current
Sense Resistor Required
z RoHS Compliant and 100% Lead (Pb)-Free
Applications
z Graph Card
z Motherboard, Desktop Servers
z IA Equipments
z Telecomm Equipments
z High Power DC-DC Regulators
Pin Configurations
(TOP VIEW)
UGATE1
BOOT1
PHASE1
NC
FB1
COMP1
NC
NC
GNDA
PHASE2
BOOT2
UGATE2
24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 16
10 15
11 14
12 13
TSSOP-24
PGND1
LGATE1
PVCC1
OCSET1/SD
OCSET2/SD
PGOOD
FB2
FBL
DRV
VCC
LGATE2
PGND2
DS9212-03 September 2005
www.richtek.com
1
1 page  
Preliminary
RT9212
Absolute Maximum Ratings (Note 1)
z Supply Voltage, VCC ------------------------------------------------------------------------------------------------- 7V
z BOOT, VBOOT - VPHASE ----------------------------------------------------------------------------------------------- 7V
z Input, Output or I/O Voltage ---------------------------------------------------------------------------------------- GND-0.3V to 7V
z Package Thermal Resistance
TSSOP-24, θJA -------------------------------------------------------------------------------------------------------- 100°C/W
z Junction Temperature ------------------------------------------------------------------------------------------------ 150°C
z Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------- 260°C
z Storage Temperature Range --------------------------------------------------------------------------------------- − 65°C to 150°C
z ESD Susceptibility (Note 2)
HBM (Human Body Mode) ----------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 3)
z Supply Voltage, VCC ------------------------------------------------------------------------------------------------- 5V ± 5 %
z Ambient Temperature Range --------------------------------------------------------------------------------------- 0°C to 70°C
z Junction Temperature Range --------------------------------------------------------------------------------------- 0°C to 125°C
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
VCC Supply Current
Nominal Supply Current
Shutdown Supply
ICC
ICCSD
OCSET1/SD, OCSET2/SD = VCC;
UGATE1 & 2, LGATE1 & 2 Open
(OCSET1/SD, OCSET2/SD) = 0V
Power-On Reset
POR Threshold
Hysteresis
VCCRTH
VOCSET1/SD, OCSET2/SD = 4.5V
VCC Rising
VCCHYS VOCSET1/SD, OCSET2/SD = 4.5V
Reference
Error Amp Reference Voltage
Tolerance
Error Amp Reference
ΔVEAR
VREF
VCC = 5V
Oscillator
Free Running Frequency
Ramp Amplitude
fOSC
ΔVOSC
VCC = 5V
V1 Error Amplifier (External Compensation)
DC Gain
Gain-Bandwidth Product
GBW
Slew Rate
SR COMP = 10pF
Min Typ Max Units
-- 5 -- mA
-- 3 -- mA
3.7 4.1 4.5
-- 0.5 --
V
V
-- -- 2
0.784 0.8 0.816
%
V
275 300 325 kHz
-- 1.9 -- VP-P
-- 90 -- dB
-- 10 -- MHz
-- 6 -- V/μs
To be continued
DS9212-03 September 2005
www.richtek.com
5
5 Page 
Preliminary
RT9212
Output Capacitor
The output capacitor is required to maintain the DC output
voltage and supply the load transient current. The capacitor
must be selected and placed carefully to yield optimal
results and should be chosen to provide acceptable ripple
on the output voltage.
The key specification for output capacitor is its ESR. Low
ESR capacitors are preferred to keep the output voltage
ripple low. The bulk capacitor's ESR will determine the
output ripple voltage and the initial voltage drop after a
high slew-rate transient. For transient response, a
combination of low value, high frequency and bulk capacitors
placed close to the load will be required. High frequency
decoupling capacitors should be placed as close to the
power pins of the load as possible. In most cases, multiple
electrolytic capacitors of small case size perform better
than a single large case capacitor.
The capacitor value must be high enough to absorb the
inductor's ripple current. The output ripple is calculated
as:
ΔVOUT = ΔIOUT × ESR
Another concern is high ESR induced output voltage ripple
may trigger UV or OV protections will cause IC shutdown.
MOSFET
The MOSFET should be selected to meet power transfer
requirements is based on maximum drain-source voltage
(VDS), gate-source drive voltage (VGS), maximum output
current, minimum on-resistance (RDS(ON)) and thermal
management.
In high-current applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The losses can be divided into
conduction and switching losses.
Conduction losses are related to the on resistance of
MOSFET, and increase with the load current. Switching
losses occur on each ON/OFF transition. The conduction
losses are the largest component of power dissipation for
both the upper and the lower MOSFETs.
For the Buck converter the average inductor current is equal
to the output load current. The conduction loss is defined
as:
PCD (high side switch) = IO2 * RDS(ON) * D
PCD (low side switch) = IO2 * RDS(ON) * (1-D)
The switching loss is more difficult to calculate. The reason
is the effect of the parasitic components and switching
times during the switching procedures such as turn-on /
turn-off delays and rise and fall times. With a linear
approximation, the switching loss can be expressed as:
PSW = 0.5 * VDS(OFF) * IO * (TRise + TFall) * F
Where
VDS(OFF) is drain to source voltage at off time,
TRise is rise time,
TFall is fall time,
F is switching frequency.
The total power dissipation in the switching MOSFET can
be calculate as:
PHigh Side Switch =
IO2 * RDS(ON)* D + 0.5 * VDS(OFF)* IO* (TRise + TFall)* F
PLow Side Switch = IO2 * RDS(ON) * (1-D)
For input voltages of 3.3V and 5V, conduction losses often
dominate switching losses. Therefore, lowering the RDS(ON)
of the MOSFETs always improves efficiency.
Feedback Compensation
The RT9212 is a voltage mode controller; the control loop
is a single voltage feedback path including an error amplifier
and PWM comparator as Figure 1 shows. In order to achieve
fast transient response and accurate output regulation, a
adequate compensator design is necessary. The goal of
the compensation network is to provide adequate phase
margin (greater than 45 degrees) and the highest 0dB
crossing frequency. And to manipulate loop frequency
response that its gain crosses over 0dB at a slope of -
20dB/dec.
DS9212-03 September 2005
www.richtek.com
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet RT9212.PDF ] | |
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