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PDF M64282FP Data sheet ( Hoja de datos )
| Número de pieza | M64282FP | |
| Descripción | Image Sensor | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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MITSUBISHI PRELIMINARY
Mitsubishi Integrated Circuit
M64282FP
Image Sensor (Artificial Retina LSI)
1. Description
M64282FP is a 128 x 128 pixel
CMOS image sensor with built-in
image processing and analog
image output tuning functions. This
device can detect an image and
process the image simultaneously
as human retinas can. M64282FP
can achieve smaller system size,
lower power consumption, and
more intelligent image processing
functions.
PIN CONFIGURATION (TOP VIEW)
RESET
READ
TSW
PGND
PVDD
VOUT
AVDD
AGND
Xck
Xrst
LOAD
DGND
DVDD
SIN
NC
START
Outline : 16C 9-B
2. Features
l Single 5.0V supply
l Low power dissipation ( Typ. 15 mW )
l Positive and negative image output
l Edge enhancement / extraction
l Output level & gain tuning
3. Application
Image input device, Gaming, Human interface for PC, etc.
4. Block Diagram
AGND AVDD
16 15
VOUT
14
PVDD
13
PGND
12
TSW
11
READ
10
RESET
9
Level
Gain
Edge
Control Control Control
LOGIC
Pixel Array
128 x 128
1
START
2
NC
3 45 67
SIN DVDD DGND LOAD Xrst
1/18
8
Xck
ver. 1.1E
5/21/98
1 page  
MITSUBISHI PRELIMINARY
(A) Xck, SIN Timing
Mitsubishi Integrated Circuit
M64282FP
Image Sensor (Artificial Retina LSI)
tcr
75%
Xck
25%
tr
tf
tWHX
tWLX
SIN
(B) Xck, LOAD Timing
tSS tHS
Xck
LOAD
tWHL
tSL tHL
5/18
ver. 1.1E
5/21/98
5 Page 
MITSUBISHI PRELIMINARY
10
11
Vertical edge mode
2-D edge mode
Mitsubishi Integrated Circuit
M64282FP
Image Sensor (Artificial Retina LSI)
11.6.3. “E” register (4 bits)
The “E” register sets the edge enhancement ratio α. The most significant bit E3
specifies edge enhancement mode or edge extraction mode: “H” for edge extraction mode
and “L” for edge enhancement mode. (In the case of normal image sensing operation, E3
should be set low) The ratio α is set as follows. 100 % means the same level as the P
signal, which is the signal of the central pixel in the 3x3 processing kernel.
Register Setting
E2 E1 E0
000
001
010
011
100
101
110
111
Edge Enhancement Ratio
50 %
75 %
100 %
125 %
200 %
300 %
400 %
500 %
11.6.4. “Z” Register (2 bits)
It calibrates the zero value by setting the dark level output signal to Vref.
Register Setting
Z1 Z0
00
10
01
Calibration
No calibration
Calibration for positive signal
Calibration for negative signal
11.6.5. “I” register (1 bit)
If the “I” register is set to “H”, the output signal is inverted. if it is set to “L”, the signal is
not inverted.
11.6.6. “C0 & C1” register (8 bits x 2)
Both C0 and C1 registers determine Exposure time; the sum of the value of C0 register
11/18
ver. 1.1E
5/21/98
11 Page | ||
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