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PDF LTC3899 Data sheet ( Hoja de datos )
| Número de pieza | LTC3899 | |
| Descripción | Buck/Buck/Boost Synchronous Controller | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Features
LTC3899
60V Low IQ, Triple
Output, Buck/Buck/Boost
Synchronous Controller
Description
n Dual Buck Plus Single Boost Synchronous Controllers
n Wide Bias Input Voltage Range: 4.5V to 60V
n Outputs Remain in Regulation Through Cold Crank
Down to a 2.2V Input Supply Voltage
n Buck and Boost Output Voltages Up to 60V
n Adjustable Gate Drive Level 5V to 10V (OPTI-DRIVE)
n No External Bootstrap Diodes Required
n Low Operating IQ: 29μA (One Channel On)
n 100% Duty Cycle for Boost Synchronous MOSFET
n Phase-Lockable Frequency (75kHz to 850kHz)
n Programmable Fixed Frequency (50kHz to 900kHz)
n Very Low Dropout Operation: 99% Duty Cycle (Bucks)
n Low Shutdown IQ: 3.6μA
n Fixed or Adjustable Boost Output Voltage Saves IQ
n Small 38-Lead 5mm × 7mm QFN and TSSOP Packages
Applications
n Automotive Always-On and Start-Stop Systems
n Distributed DC Power Systems
n Multioutput Buck-Boost Applications
The LTC®3899 is a high performance triple output (buck/
buck/boost) DC/DC switching regulator controller that
drives all N-channel synchronous power MOSFET stages.
The constant frequency current mode architecture allows
a phase-lockable frequency of up to 850kHz. The LTC3899
operates from a wide 4.5V to 60V input supply range.
When biased from the output of the boost converter or
another auxiliary supply, the LTC3899 can operate from
an input supply as low as 2.2V after start-up.
The gate drive for the LTC3899 can be programmed from
5V to 10V to allow the use of logic-level or standard-level
FETs and to maximize efficiency. Internal switches in the
top gate drivers eliminate the need for external bootstrap
diodes. The 29μA no-load quiescent current extends op-
erating run time in battery-powered systems. OPTI-LOOP®
compensation allows the transient response to be optimized
over a wide range of output capacitance and ESR values.
L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, Linear Technology and the Linear logo are
registered trademarks of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents including 5481178, 5705919, 5929620,
6144194, 6177787, 6580258.
Typical Application
High Efficiency Wide Input Range Dual 5V/8.5V Converter
VOUT3
REGULATED AT 10V
WHEN VIN < 10V
FOLLOWS VIN WHEN
VIN > 10V
33µF
VIN
2.2V TO 60V
(START-UP
ABOVE 5V)
3mΩ 1.2µH
33µF
4.7µF
RUN1, 2, 3 VBIAS
VFB3 TG1 0.1µF
0.1µF
0.1µF
TG3 BOOST1
SW1
BOOST3
SW3 BG1
LTC3899
BG3 SSEENNSSEE11+–
SSEENNSSEE33–+
VFB1
DRVCC
INTVCC
TG2 0.1µF
ITH1,2,3 BOOST2
SW2
BG2
DRVSET
SENSE2+
SENSE2–
VPRG3
GND
VFB2
4.9µH 9mΩ
VOUT1
5V
5A
357k
68.1k
220µF
6.5µH 15mΩ
VOUT2
8.5V
3A
649k
68.1k
68µF
3899 TA01a
For more information www.linear.com/LTC3899
Efficiency vs Output Current
95 VIN = 12V
94
VOUT = 5V
Burst Mode OPERATION
93
92
91
90
89
88
0.01
GATE DRIVE (DRVCC)
5V
6V
8V
10V
0.1 1
OUTPUT CURRENT(A)
10
3899 TA01b
3899f
1
1 page  
LTC3899
E lectrical Characteristics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VBIAS = 12V, VRUN1,2,3 = 5V, VEXTVCC = 0V, VDRVSET =
0V, VPRG3 = Float unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
BDSW1,2,3
TG1,2,3 tr
TG1,2,3 tf
BG1,2,3
BG1,2,3
ttrf
TG1,2/BG1,2
t1D
BG1,2/TG1,2
t1D
TG3/BG3 t1D
BOOST to DRVCC Switch On-Resistance
TG Transition Time:
Rise Time
Fall Time
BG Transition Time:
Rise Time
Fall Time
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
CH3 Top Gate Off to Bottom Gate On Delay
Bottom Switch-On Delay Time
VSW = 0V, VDRVSET = INTVCC
(Note 6) VDRVSET = INTVCC
CLOAD = 3300pF
CLOAD = 3300pF
(Note 6) VDRVSET = INTVCC
CCLLOOAADD
=
=
3300pF
3300pF
CLOAD = 3300pF Each Driver, VDRVSET = INTVCC
CLOAD = 3300pF Each Driver, VDRVSET = INTVCC
CLOAD = 3300pF Each Driver, VDRVSET = INTVCC
3.7
25
15
25
15
55
50
85
Ω
ns
ns
ns
ns
ns
ns
ns
BG3/TG3 t1D
CH3 Bottom Gate Off to Top Gate On Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF Each Driver, VDRVSET = INTVCC
80
ns
tON(MIN)1,2
Buck Minimum On-Time
tON(MIN)3
Boost Minimum On-Time
DRVCC Linear Regulator
VDRVCC(INT) DRVCC Voltage from Internal VBIAS LDO
VLDOREG(INT)
VDRVCC(EXT)
DRVCC Load Regulation from VBIAS LDO
DRVCC Voltage from Internal EXTVCC LDO
VLDOREG(EXT)
VEXTVCC
DRVCC Load Regulation from Internal
EXTVCC LDO
EXTVCC LDO Switchover Voltage
VLDOHYS
EXTVCC Hysteresis
VDRVCC(50kΩ) Programmable DRVCC
VDRVCC(70kΩ) Programmable DRVCC
VDRVCC(90kΩ) Programmable DRVCC
Oscillator and Phase-Locked Loop
(Note 7) VDRVSET = INTVCC
(Note 7) VDRVSET = INTVCC
VEXTVCC = 0V
7V < VBIAS < 60V, DRVSET = 0V
11V < VBIAS < 60V, DRVSET = INTVCC
ICC = 0mA to 50mA, VEXTVCC = 0V
7V < VEXTVCC < 13V, DRVSET = 0V
11V < VEXTVCC < 13V, DRVSET = INTVCC
ICC = 0mA to 50mA, VEXTVCC = 8.5V,
VDRVSET = 0V
EXTVCC Ramping Positive
DRVSET
DRVSET
=
=
I0NVToVrCCRDRVSET
≤
100kΩ
RDRVSET = 50kΩ, VEXTVCC = 0V
RDRVSET = 70kΩ, VEXTVCC = 0V
RDRVSET = 90kΩ, VEXTVCC = 0V
80 ns
120 ns
5.8 6.0 6.2
9.6 10.0 10.4
0.9 2.0
5.8 6.0 6.2
9.6 10.0 10.4
0.7 2.0
4.5 4.7 4.9
7.4 7.7 8.0
250
5.0
6.4 7.0 7.6
9.0
V
V
%
V
V
%
V
V
mV
V
V
V
f25kΩ
Programmable Frequency
f65kΩ
Programmable Frequency
f105kΩ
Programmable Frequency
fLOW Low Fixed Frequency
fHIGH High Fixed Frequency
fSYNC
Synchronizable Frequency
PLLIN VIH
PLLIN VIL
PLLIN/MODE Input High Level
PLLIN/MODE Input Low Level
BOOST3 Charge Pump
RFREQ =25kΩ, PLLIN/MODE = DC Voltage
RFREQ = 65kΩ, PLLIN/MODE = DC Voltage
RFREQ = 105kΩ, PLLIN/MODE = DC Voltage
VFREQ = 0V, PLLIN/MODE = DC Voltage
VFREQ = INTVCC, PLLIN/MODE = DC Voltage
PLLIN/MODE = External Clock
PLLIN/MODE = External Clock
PLLIN/MODE = External Clock
105
375 440 505
835
320 350 380
485 535 585
l 75
850
l 2.5
l
0.5
kHz
kHz
kHz
kHz
kHz
kHz
V
V
IBST3
BOOST3 Charge Pump Available Output
Current
FREQ = 0V, PLLIN/MODE
VBOOST3 = 16.5V, VSW3 =
1=2IVNTVCC
VBOOST3 = 19V, VSW3 = 12V
75 µA
35 µA
3899f
For more information www.linear.com/LTC3899
5
5 Page 
LTC3899
Pin Functions (QFN/TSSOP)
FREQ (Pin 1/ Pin 5): The frequency control pin for the
internal VCO. Connecting this pin to GND forces the VCO
to a fixed low frequency of 350kHz. Connecting this pin
to INTVCC forces the VCO to a fixed high frequency of
535kHz. Other frequencies between 50kHz and 900kHz can
be programmed using a resistor between FREQ and GND.
The resistor and an internal 20µA source current create a
voltage used by the internal oscillator to set the frequency.
PLLIN/MODE (Pin 2/Pin 6): External Synchronization
Input to Phase Detector and Forced Continuous Mode
Input. When an external clock is applied to this pin, the
phase-locked loop will force the rising TG1 signal to be
synchronized with the rising edge of the external clock,
and the regulators will operate in forced continuous mode.
When not synchronizing to an external clock, this input,
which acts on all three controllers, determines how the
LTC3899 operates at light loads. Pulling this pin to ground
selects Burst Mode operation. An internal 100k resistor to
ground also invokes Burst Mode operation when the pin is
floated. Tying this pin to INTVCC forces continuous inductor
current operation. Tying this pin to a voltage greater than
1.1V and less than INTVCC – 1.3V selects pulse-skipping
operation. This can be done by connecting a 100k resistor
from this pin to INTVCC.
INTVCC (Pin 8/Pin 12): Output of the Internal 5V Low
Dropout Regulator. The low voltage analog and digital
circuits are powered from this voltage source. A low ESR
0.1µF ceramic bypass capacitor should be connected
between INTVCC and GND, as close as possible to the IC.
RUN1, RUN2, RUN3 (Pins 9, 10, 11/ Pins 13, 14, 15):
Run Control Inputs for Each Controller. Forcing any of these
pins below 1.2V shuts down that controller. Forcing all of
these pins below 0.7V shuts down the entire LTC3899,
reducing quiescent current to approximately 3.6µA.
DRVSET (Pin 16/Pin 20): Sets the regulated output volt-
age of the DRVCC LDO regulator. Connecting this pin to
GND sets DRVCC to 6V whereas connecting it to INTVCC
sets DRVCC to 10V. Voltages between 5V and 10V can be
programmed by placing a resistor (50k to 100k) between
the DRVSET pin and GND. The DRVSET pin also determines
the higher or lower DRVCC UVLO and EXTVCC switchover
thresholds, as listed on the Electrical Characteristics table.
Connecting DRVSET to GND or programming DRVSET with
a resistor chooses the lower thresholds whereas tying
DRVSET to INTVCC chooses the higher thresholds. When
programming DRVSET with a resistor, do not choose a
resistor value less than 50k (unless shorting DRVSET to
GND) or higher than 100k.
DRVCC (Pin 22/Pin 26): Output of the Internal or External
Low Dropout (LDO) Regulator. The gate drivers are pow-
ered from this voltage source. The DRVCC voltage is set
by the DRVSET pin. Must be decoupled to ground with a
minimum of 4.7µF ceramic or other low ESR capacitor.
Do not use the DRVCC pin for any other purpose.
EXTVCC (Pin 23/Pin 27): External Power Input to an Inter-
nal LDO Connected to DRVCC. This LDO supplies DRVCC
power, bypassing the internal LDO powered from VBIAS
whenever EXTVCC is higher than its switchover threshold
(4.7V or 7.7V depending on the DRVSET pin). See EXTVCC
Connection in the Applications Information section. Do not
float or exceed 14V on this pin. Do not connect EXTVCC to
a voltage greater than VBIAS. Connect to GND if not used.
VBIAS (Pin 24/Pin 28): Main Supply Pin. A bypass capacitor
should be tied between this pin and the GND pin.
BG1, BG2, BG3 (Pins 29, 21, 25/Pins 33, 25, 29): High
Current Gate Drives for Bottom N-Channel MOSFETs.
Voltage swing at these pins is from ground to DRVCC.
BOOST1, BOOST2, BOOST3 (Pins 30, 20, 26/Pins 34,
24, 30): Bootstrapped Supplies to the Topside Floating
Drivers. Capacitors are connected between the BOOST and
SW pins. Voltage swing at BOOST1 and BOOST2 pins is
from approximately DRVCC to (VIN1,2 + DRVCC). Voltage
swing at BOOST3 is from DRVCC to (VOUT3 + DRVCC).
SW1, SW2, SW3 (Pins 31, 19, 28/Pins 34, 24, 30):
Switch Node Connections to Inductors.
TG1, TG2, TG3 (Pins 32, 18, 27/Pins 36, 22, 31): High
Current Gate Drives for Top N-Channel MOSFETs. These are
the outputs of floating drivers with a voltage swing equal
to DRVCC superimposed on the switch node voltage SW.
For more information www.linear.com/LTC3899
3899f
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC3899.PDF ] | |
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