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PDF Pm25LV010A Data sheet ( Hoja de datos )
| Número de pieza | Pm25LV010A | |
| Descripción | Serial Flash Memory | |
| Fabricantes | Programmable Microelectronics | |
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FEATURES
Pm25LV512A / 010A / 020 / 040
512 Kbit /1 Mbit / 2 Mbit / 4 Mbit 3.0 Volt-only,
Serial Flash Memory With 100 MHz SPI Bus Interface
• Single Power Supply Operation
- Low voltage range: 2.7 V - 3.6 V
• Memory Organization
- Pm25LV512A: 64K x 8 (512 Kbit)
- Pm25LV010A: 128K x 8 (1 Mbit)
- Pm25LV020: 256K x 8 (2 Mbit)
- Pm25LV040: 512K x 8 (4 Mbit)
• Cost Effective Sector/Block Architecture
- 512Kb : Uniform 4Kbyte sectors / Two uniform
32Kbyte blocks
- 1Mb : Uniform 4Kbyte sectors / Four uniform
32Kbyte blocks
- 2Mb : Uniform 4Kbyte sectors / Four uniform
64Kbyte blocks
- 4Mb : Uniform 4Kbyte sectors / Eight uniform
64Kbyte blocks
- Bottom sector is configurable as one 4Kbyte sector
or four 1Kbyte sectors (except Pm25LV512A)
• Serial Peripheral Interface (SPI) Compatible
- Supports SPI Modes 0 (0,0) and 3 (1,1)
- Maximum 33 MHz clock rate for normal read
- Maximum 100 MHz clock rate for fast read
• Page Program (up to 256 Bytes) Operation
- Typical 2 ms per page program
• Sector, Block or Chip Erase Operation
- Typical 60 ms sector, block or chip erase
• Software Write Protection
- The Block Protect (BP2, BP1, BP0) bits allow partial
or entire memory to be configured as read-only
• Hardware Write Protection
- Protect and unprotect the device from write operation
by Write Protect (WP#) Pin
• Low Power Consumption
- Typical 10 mA active read current
- Typical 15 mA program/erase current
• High Product Endurance
- Guarantee 200,000 program/erase cycles per single
sector
- Minimum 20 years data retention
• Industrial Standard Pin-out and Package
- 8-pin 150mil SOIC
- 8-pin 208mil SOIC for Pm25LV040
- 8-pin 300mil PDIP for Pm25LV040
- 8-contact WSON
- 8-pin TSSOP for Pm25LV512A
GENERAL DESCRIPTION
The Pm25LV512A/010A/020/040 are 512Kbit/1 Mbit/2 Mbit/4 Mbit 3.0 Volt-only Serial Peripheral Interface (SPI)
Flash memories. The devices are designed to support 33 MHz fastest clock rate in the industry in normal read
mode, 100 MHz in fast read mode and the bottom 4 Kbyte sector into four smaller 1 Kbyte sectors features(except
Pm25LV512A). The devices use a single low voltage, ranging from 2.7 Volt to 3.6 Volt, power supply to perform
read, erase and program operations. The devices can be programmed in standard EPROM programmers as well.
The Pm25LV512A/010A is backward compatible to their predecessors Pm25LV512/010.
The Pm25LV512A/010A/020/040 are accessed through a 4-wire SPI Interface consists of Serial Data Input (Sl),
Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. The devices support page program
mode, 1 to 256 bytes data can be programmed into the memory in one program operation. The memory of
Pm25LV512A/010A is divided into uniform 4 Kbyte sectors or uniform 32 Kbyte blocks (sector group - consists of
eight adjacent sectors) for data or code storage. The memory of Pm25LV020/040 are divided into uniform 4 Kbyte
sectors or uniform 64 Kbyte blocks (sector group - consists of sixteen adjacent sectors). The devices have an
innovative feature to configure the bottom 4 Kbyte sector into four smaller 1 Kbyte sectors for eliminating additional
serial EEPROM needed for storing data. This is a further cost reduction for overall system.
The Pm25LV512A/010A/020/040 are manufactured on pFLASH™’s advanced nonvolatile technology. The devices
are offered in 8-pin SOIC, 8-contact WSON and 8-pin PDIP (Pm25LV040) packages with operation frequency up to
100 MHz in fast read and 33 MHz in normal read mode.
Chingis Technology Corporation
1 Issue Date: Feb., 2009, Rev: 3.5
1 page  
Pm25LV512A/010A/020/040
SPI MODES DESCRIPTION
Multiple Pm25LV512A/010A/020/040 devices can be se-
rially connected onto the SPI serial bus controlled by a
SPI Master i.e. microcontroller as shown in Figure 1.
The devices support either of the two SPI modes:
Mode 0 (0, 0)
Mode 3 (1, 1)
The difference between these two modes is the clock
polarity when the SPI master is in Stand-by mode: the
serial clock remains at “0” (SCK = 0) for Mode 0 and the
clock remains at “1” (SCK = 1) for Mode 1. Please refer
to Figure 2. For both modes, the input data is latched on
the rising edge of Serial Clock (SCK), and the output
data is available from the falling edge of SCK.
Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
SPI Interface with
(0, 0) or (1, 1)
SDO
SDI
SCK
SCK SO SI
SCK SO SI
SCK SO SI
SPI Master
(i.e. Microcontroller)
CS3 CS2 CS1
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CE# WP# HOLD# CE# WP# HOLD# CE# WP# HOLD#
Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven, High or Low as appropriate.
Figure 2. SPI Modes Supported
Mode 0 (0, 0) SCK
Mode 3 (1, 1) SCK
SI MSB
SO
MSB
Chingis Technology Corporation
5 Issue Date: Feb., 2009, Rev: 3.5
5 Page 
Pm25LV512A/010A/020/040
DEVICE OPERATION (CONTINUED)
READ PRODUCT IDENTIFICATION OPERATION
Table 9. Product Identification
The Read Product Identification (RDID) instruction al-
lows the user to read the manufacturer and product ID of
the devices. Refer to Table 9 Product Identification for
pFLASH™ manufacturer ID and device ID. The RDID in-
struction code is followed by three dummy bytes, each
bit being latched-in on SI during the rising edge of SCK.
Then the first manufacturer ID (9Dh) is shifted out on SO
with the MSB first, followed by the device ID and the
second manufacturer ID (7Fh), each bit been shifted out
during the falling edge of SCK. If the CE# stays low after
the last bit of second manufacturer ID is shifted out, the
manufacturer ID and device ID will be looping until the
pulled high of CE# signal.
Product Identification
Manufacturer ID
First Byte
Second Byte
Device ID:
Pm25LV512A
Pm25LV010A
Pm25LV020
Pm25LV040
Data
9Dh
7Fh
7Bh
7Ch
7Dh
7Eh
Figure 3. Read Product Identification Sequence
CE#
SCK
SI
01
78 9
31
INSTRUCTION 3 Dummy Bytes
1010 1011b
38 39
46 47
54
HIGH IMPEDANCE
SO
Manufacture ID1
Device ID
Manufacture ID2
Chingis Technology Corporation
11 Issue Date: Feb., 2009, Rev: 3.5
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet Pm25LV010A.PDF ] | |
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