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PDF DSP56321 Data sheet ( Hoja de datos )
| Número de pieza | DSP56321 | |
| Descripción | 24-Bit Digital Signal Processor | |
| Fabricantes | Freescale Semiconductor | |
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Freescale Semiconductor
Technical Data
DSP56321
Rev. 11, 2/2005
DSP56321
24-Bit Digital Signal Processor
3 16 6 6
Memory Expansion Area
SCI
Triple
Timer
Address
Generation
Unit
Six Channel
DMA Unit
Bootstrap
ROM
Internal
Data
Bus
Switch
Clock
Generator
PLL
EXTAL
XTAL
RESET
PINIT/NMI
HI08
ESSI
EFCOP
Peripheral
Expansion Area
Program
RAM
32 K × 24 bits
or
31 K × 24 bits
and
Instruction
Cache
1024 × 24 bits
X Data
RAM
80 K × 24 bits
Y Data
RAM
80 K × 24 bits
YAB
XAB
PAB
DAB
External
Address
Bus
Switch
18
Address
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
External
Bus
Interface
and
I - Cache
Control
10
Control
External
Data
Bus
Switch
24
Data
Program
Interrupt
Controller
Program
Decode
Controller
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Program
Address
Generator
Power
Management
Data ALU
24 × 24 + 56 →56-bit MAC
Two 56-bit Accumulators
JTAG
56-bit Barrel Shifter
OnCE™
5
DE
Figure 1. DSP56321 Block Diagram
The DSP56321 is intended
for applications requiring a
large amount of internal
memory, such as networking
and wireless infrastructure
applications. The onboard
EFCOP can accelerate
general filtering applications,
such as echo-cancellation
applications, correlation, and
general-purpose convolution-
based algorithms.
What’s New?
Rev. 11 includes the following
changes:
• Adds lead-free packaging and
part numbers.
The Freescale DSP56321, a member of the DSP56300 DSP family, supports networking, security encryption, and
home entertainment using a high-performance, single-clock-cycle-per- instruction engine (DSP56000 code-
compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA) controller
(see Figure 1).
The DSP56321 offers 275 million multiply- accumulates per second (MMACS) performance, attaining 550
MMACS when the EFCOP is in use. It operates with an internal 275 MHz clock with a 1.6 volt core and
independent 3.3 volt input/output (I/O) power. By operating in parallel with the core, the EFCOP provides overall
enhanced performance and signal quality with no impact on channel throughput or total channel support. This
device is pin-compatible with the Freescale DSP56303, DSP56L307, DSP56309, and DSP56311.
© Freescale Semiconductor, Inc., 2001, 2005. All rights reserved.
1 page  
Product Documentation
The documents listed in Table 2 are required for a complete description of the DSP56321 device and are necessary
to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale
semiconductor sales office, or a Freescale Semiconductor Literature Distribution Center. For documentation
updates, visit the Freescale DSP website. See the contact information on the back cover of this document.
Table 2. DSP56321 Documentation
Name
Description
Order Number
DSP56321
Detailed functional description of the DSP56321 memory configuration,
Reference Manual operation, and register programming
DSP56300 Family Detailed description of the DSP56300 family processor core and instruction set
Manual
Application Notes Documents describing specific applications or optimized device operation
including code examples
DSP56321RM
DSP56300FM
See the DSP56321 product website
Freescale Semiconductor
DSP56321 Technical Data, Rev. 11
v
5 Page 
External Memory Expansion Port (Port A)
Table 1-7. External Bus Control Signals (Continued)
Signal Name
Type
TA Input
BR Output
BG Input
BB Input/ Output
State During
Reset, Stop, or
Wait
Signal Description
Ignored Input
Transfer Acknowledge—If the DSP56321 is the bus master and there is no
external bus activity, or the DSP56321 is not the bus master, the TA input is
ignored. The TA input is a data transfer acknowledge (DTACK) function that can
extend an external bus cycle indefinitely. Any number of wait states (1,
2. . .infinity) can be added to the wait states inserted by the bus control register
(BCR) by keeping TA deasserted. In typical operation, TA is deasserted at the
start of a bus cycle, is asserted to enable completion of the bus cycle, and is
deasserted before the next bus cycle. The current bus cycle completes one
clock period after TA is asserted synchronous to CLKOUT. The number of wait
states is determined by the TA input or by the BCR, whichever is longer. The
BCR can be used to set the minimum number of wait states in external bus
cycles.
To use the TA functionality, the BCR must be programmed to at least one wait
state. A zero wait state access cannot be extended by TA deassertion;
otherwise, improper operation may result.
Reset: Output
(deasserted)
State during
Stop/Wait
depends on BRH
bit setting:
• BRH = 0: Output
(deasserted)
• BRH = 1:
Maintains last
state (that is, if
asserted, remains
asserted)
Bus Request—Asserted when the DSP requests bus mastership. BR is
deasserted when the DSP no longer needs the bus. BR may be asserted or
deasserted independently of whether the DSP56321 is a bus master or a bus
slave. Bus “parking” allows BR to be deasserted even though the DSP56321 is
the bus master. (See the description of bus “parking” in the BB signal
description.) The bus request hold (BRH) bit in the BCR allows BR to be
asserted under software control even though the DSP does not need the bus.
BR is typically sent to an external bus arbitrator that controls the priority,
parking, and tenure of each master on the same external bus. BR is affected
only by DSP requests for the external bus, never for the internal bus. During
hardware reset, BR is deasserted and the arbitration is reset to the bus slave
state.
Ignored Input
Bus Grant—Asserted by an external bus arbitration circuit when the DSP56321
becomes the next bus master. When BG is asserted, the DSP56321 must wait
until BB is deasserted before taking bus mastership. When BG is deasserted,
bus mastership is typically given up at the end of the current bus cycle. This may
occur in the middle of an instruction that requires more than one external bus
cycle for execution.
Ignored Input
To ensure proper operation, the user must set the asynchronous bus arbitration
enable (ABE) bit (Bit 13) in the Operating Mode Register. When this bit is set,
BG and BB are synchronized internally. This adds a required delay between the
deassertion of an initial BG input and the assertion of a subsequent BG input.
Bus Busy—Indicates that the bus is active. Only after BB is deasserted can the
pending bus master become the bus master (and then assert the signal again).
The bus master may keep BB asserted after ceasing bus activity regardless of
whether BR is asserted or deasserted. Called “bus parking,” this allows the
current bus master to reuse the bus without rearbitration until another device
requires the bus. BB is deasserted by an “active pull-up” method (that is, BB is
driven high and then released and held high by an external pull-up resistor).
Notes: 1. See BG for additional information.
2. BB requires an external pull-up resistor.
Freescale Semiconductor
DSP56321 Technical Data, Rev. 11
1-5
11 Page | ||
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