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PDF LX7730MFQ-EQ Data sheet ( Hoja de datos )
| Número de pieza | LX7730MFQ-EQ | |
| Descripción | 64 Analog Input RAD Tolerant Telemetry Controller | |
| Fabricantes | Microsemi Corporation | |
| Logotipo |  |
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Preliminary Datasheet
LX7730
64 Analog Input RAD Tolerant Telemetry
Controller
Description
The LX7730 is a spacecraft telemetry manager IC that
functions as a companion to the FPGA. The LX7730
contains a 64 universal input multiplexer that can be
configured as a mix of differential or single ended sensor
inputs. There is a programmable current source that can
be directed to any of the 64 universal inputs. The
universal inputs can be sampled with a 12 bit analog-to-
digital converter at a sample rate up to 25kHz. The
universal inputs can also function as variable bi-level
inputs with the threshold set by an internal 8 bit digital-to-
analog converter. There is an additional 10 bit digital-to-
analog current DAC with complementary outputs. Finally
there are 8 fixed threshold bi-level inputs.
The LX7730 is register programmable with 17
addressable eight bit registers. Two options are
available for communication with the host FPGA. First
there is an eight bit parallel bus with 5 address bits and a
read/write bit that can communicate at a speed of up to
25MHz. The second option is a pair of 50MBPS SPI
interfaces that can support redundant (alternating not
simultaneous) communication to two different hosts.
The LX7730 offers 1 kV ESD pin protection on all CH#
pins and 2kV on the other pins. The dielectric isolated
process is failsafe. The LX7730 has enable registers that
allow most of the device to be shut down to reduce power
consumption and supports cold sparing on its signal pins.
The controller is designed for use in rugged
environments. It is packaged in a 132 pin ceramic quad
flat pack and operates over a -55°C to 125°C
temperature range. It is radiation tolerant to 100krad TID
and 50krad ELDRs as well as Single event latch up.
Features
64 channel MUX
Break-before-make switching
25kSPS 12 bit ADC
2% Precision Adjustable Current Source
1% Precision 5.00V Source
Threshold Monitoring
8 x Bi-level Logic
10 bit DAC
Parallel or Dual SPI Interface
Radiation Tolerant: 100krad TID, 50kad ELDRS
Applications
Spacecraft Health Monitoring
Attitude Control
Payload Equipment
Main power
Internal LDOs
and Charge
Pump
VREF
Parallel
SPI_A
FPGA
SPI_B
Parallel
Interface
and
Registers
8 Current
Levels
12 Bit
ADC
64
Channel
Sensor
+ MUX
- Level Detect
8 Bit
DAC
10 Bit Current
DAC
+ 8 Bi-Level Inputs
- 2.5V
LX7730
Figure 1 · Product Highlight
LX7730 rev 0.9.2
©2015 Microsemi
1
1 page  
Pin Description
Pin Number
44-51
53-118
119
121
122
123
124
125
126
127
128
129
130
131
Pin Designator
Description
be attached from this pin to AGND.
BLI#
CH#
SE_RTN
VCC
PCP
NCP
VEE
MINUS2V
/EXT_VEE
/EXT_REF
TEST_MODE
PROGSUPPLY
/SPI_A
/SPI_B
Fixed threshold Bi Level Signal Input – Signal Input Pin – This pin is fixed
threshold bi-level input: channel 8 (pin 44) decreasing to channel 1 (pin 51).
General purpose sensor interface – Signal I/O - This pin provides input for
the sensor interface or output for the adjustable current source. Channel 1
(pin 53) to channel 64 (pin 118). A few AGND pins are interspersed.
Single Ended Sensor Return – Signal Pin – This pin is used as a common
return for single ended sensor inputs.
Main power supply – Power Input – This pin is the main power supply. The
internal (VEE and +5V) voltage regulators are powered from this rail.
Charge Pump Transfer Capacitor Positive Terminal – Power Pin – This pin is
used for the charge pump used to generate VEE; it swings between GND
and VCC. Connect a 0.47µF capacitor between this pin and the NCP pin.
Charge Pump Transfer Capacitor Negative Terminal – Power Pin – This pin
is used for the charge pump used to generate VEE; it swings between GND
and VEE. Connect a 0.47µF capacitor between this pin and the PCP pin.
Negative power rail – Power I/O – This pin is the negative voltage power rail.
It can be generated internally (using the charge pump) or supplied from an
external source connected to this pin. A bypass capacitor to GND is
required. The charge pump can be disabled by shorting the /VEE_EN pin to
GND.
2V Intermediate power rail – Power Pin – This pin is the low voltage power
rail. It is generated internally using a linear regulator connected to the VEE
rail. A bypass capacitor to GND is required.
Enable external VEE – Programming pin – This pin disables the VEE charge
pump if it is shorted to ground. If high, the VEE charge pump is enabled.
There is a weak pull-up on this pin.
Enable External Reference – Programming pin – This pin disables the
internal voltage reference when it is shorted to ground. If high, the internally
generated voltage reference is used. There is a weak pull-up on this pin.
Test and Trim Pins – Programming Pins - This pins is used for in package
trim and testing of the device. In normal use they should be left open.
Trim Power Supply – Power Pin – This pin is used to blow fusible links when
trimming the part in package at the factory. In normal application this pin
should be shorted to +5V.
Enable SPI Interface A – Logic Input – This pin is active low. Asserting this
pin enables the SPI channel A interface and deactivates the parallel
interface and SPI channel B. If both /SPI_A and /SPI_B pins are low, the
first asserted pin dominates. There is a weak pull-up on this pin.
Enable SPI Interface B – Logic Input – This pin is active low. Asserting this
pin enables the SPI channel B interface and deactivates the parallel
interface and SPI channel A. If both /SPI_A and /SPI_B pins are low, the
first asserted pin dominates. There is a weak pull-up on this pin.
LX7730 rev 0.9.1
©2015 Microsemi
5
5 Page 
Electrical Characteristics
Symbol
VADC_IN
Parameters
Integral nonlinearity
Test Conditions/Comments
from 15% to 75% of full scale
VADC_IN
Differential nonlinearity
IADC_IN
Leakage current
Internal amplifier in Hi-Z state; ADC
not converting
tCONV
Conversion Time
tACQU
Acquisition Time
tSAMP
Sample Period
Adjustable threshold Bi-Level MUX and DAC
VCH#
Threshold DAC Max
Output
VCH#
Threshold DAC LSB
Weight
VCH#
VCH#
DAC Integral Linearity
Offset error
Using codes 20 to 255, best fit
straight line
VCH#
DAC Differential Linearity
VCH#
Settling Time
VCH#
Hysteresis
Rising threshold = DAC output;
falling threshold has hysteresis
VCH#
Propagation Delay
10 Bit Current DAC
IDAC_P
Full scale
IDAC_N
Full scale
IDAC_P,N
LSB Weight
IDAC_ P,N Integral Nonlinearity
IDAC_ P,N Differential Nonlinearity
VDAC_ P,N Compliance Range
IDAC_ P,N
Settling
Fixed Threshold Bi-Level Inputs
VBLI#
Threshold
(Rising Voltage)
Internal reference
With external 2.50V reference
VBLI#
Hysteresis
Only falling threshold has hysteresis;
Rising is dead on
VBLI#
Voltage Clamp
(power applied)
Clamp Current = 1mA (into pin)
Clamp Current = 1mA (out of pin)
IBLI# Bias Current
VBLI1 = 0V to 5V
IBLI# Leakage Current
VBLI1 = 0V to 5V; IC powered off
tBLI# Propagation Delay
High to low transition
Low to high transition
VBL_TH
Ext Threshold Pin Range
IBL_TH
Threshold Pin Leakage VBL_TH = 0V to 5V
Min
-13
-4
-10
4.95
-0.75
-0.75
75
-2.06
-1
-0.95
0
2.4
2.4
75
15
-22
-1
-1
0.5
-1
Typ
0
0
0
38
13
25
5
19.5
38
150
-2.00
0
-1.953
0
0
1.5
2.5
2.5
150
17
-17
0
0
2
0.5
0
Max
13
4
10
5.05
0.75
0.75
2
200
2
-1.94
1
0.95
3
2.6
2.6
200
22
-15
1
1
4.6
1
Units
LSB
LSB
µA
µs
µs
µs
V
mV
LSB
mV
LSB
µs
mV
µs
mA
mA
µA
LSB
LSB
V
µs
V
mV
V
µA
µA
µs
V
µA
LX7730 rev 0.9.1
©2015 Microsemi
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LX7730MFQ-EQ.PDF ] | |
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