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PDF LPC1224 Data sheet ( Hoja de datos )
| Número de pieza | LPC1224 | |
| Descripción | 32-bit ARM Cortex-M0 microcontroller | |
| Fabricantes | NXP Semiconductors | |
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LPC122x
32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash and
8 kB SRAM
Rev. 1.1 — 21 February 2011
Objective data sheet
1. General description
The LPC122x extend NXP's 32-bit ARM microcontroller continuum and target a wide
range of industrial applications in the areas of factory and home automation. Benefitting
from the ARM Cortex-M0 Thumb instruction set, the LPC122x have up to 50 % higher
code density compared to common 8/16-bit microcontroller performing typical tasks. The
LPC122x also feature an optimized ROM-based divide library for Cortex-M0, which offers
several times the arithmetic performance of software-based libraries, as well as highly
deterministic cycle time combined with reduced flash code size. The ARM Cortex-M0
efficiency also helps the LPC122x achieve lower average power for similar applications.
The LPC122x operate at CPU frequencies of up to 45 MHz.They offer a wide range of
flash memory options, from 32 kB to 128 kB. The small 512-byte page erase of the flash
memory brings multiple design benefits, such as finer EEPROM emulation, boot-load
support from any serial interface and ease of in-field programming with reduced on-chip
RAM buffer requirements.
The peripheral complement of the LPC122x includes a 10-bit ADC, two comparators with
output feedback loop, two UARTs, one SSP/SPI interface, one I2C-bus interface with
Fast-mode Plus features, a Windowed Watchdog Timer, a DMA controller, a CRC engine,
four general purpose timers, a 32-bit RTC, a 1 % internal oscillator for baud rate
generation, and up to 55 General Purpose I/O (GPIO) pins.
2. Features and benefits
www.DataSheet4U.com
Processor core
ARM Cortex-M0 processor, running at frequencies of up to 45 MHz (one wait state
from flash) or 30 MHz (zero wait states from flash). The LPC122x have a high
score of over 45 in CoreMark CPU performance benchmark testing, equivalent to
1.51/MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Serial Wire Debug (SWD).
System tick timer.
Memory
Up to 8 kB SRAM.
Up to 128 kB on-chip flash programming memory.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
Includes ROM-based 32-bit integer division routines.
Clock generation unit
1 page  
NXP Semiconductors
5. Block diagram
LPC122x
32-bit ARM Cortex-M0 microcontroller
SWD
LPC122x
GPIO ports
TEST/DEBUG
INTERFACE
ARM
CORTEX-M0
system
bus
slave
HIGH-SPEED
GPIO
XTALIN
XTALOUT
RESET
IRC, OSCILLATORS
BOD
POR
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
clocks and controls
MICRO DMA
CONTROLLER
32/48/64/80/
96/128 kB
FLASH
4/8 kB
SRAM
master
slave
slave
AHB-LITE BUS
slave
slave
ROM
slave
AHB-APB
BRIDGE
CRC
ENGINE
CLKOUT
SCK
SSEL
MISO
MOSI
RXD0
TXD0
DTR0, DSR0, CTS0,
DCD0, RI0, RTS0
RXD1
TXD1
SCL
SDA
4 × MAT
4 × CAP
4 × MAT
4 × CAP
2 × MAT
2 × CAP
2 × MAT
2 × CAP
SSP/SPI
UART0 RS-485
UART1
I2C
32-bit COUNTER/TIMER 0
32-bit COUNTER/TIMER 1
16-bit COUNTER/TIMER 0
16-bit COUNTER/TIMER 1
www.DataSheet4U.com
Fig 1. LPC122x block diagram
10-bit ADC
COMPARATOR0/1
WINDOWED WDT
RTC
IOCONFIG
32 kHz OSCILLATOR
SYSTEM CONTROL
MICRO DMA REGISTERS
AD[7:0]
ACMP0_I[3:0]
ACMP1_I[3:0]
ACMP0_O
ACMP1_O
VREF_CMP
RTCXOUT
RTCXIN
Grey-shaded blocks represent peripherals
with connection to the micro DMA
002aaf269
LPC122X
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 21 February 2011
© NXP B.V. 2011. All rights reserved.
5 of 60
5 Page 
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
Table 3.
Symbol
LPC122x pin description …continued
Start Type Reset Description
logic
state
input
[1]
PIO0_27/ACMP0_O 12 12 [7] no
PIO0_28/ACMP1_O/
CT16B0_CAP0/
CT16B0_MAT0
13 17 [7] no
PIO0_29/ROSC/
CT16B0_CAP1/
CT16B0_MAT1
14 18 [7] no
R/PIO0_30/AD0
34 46 [5] no
R/PIO0_31/AD1
35 47 [5] no
PIO1_0 to PIO1_6
R/PIO1_0/AD2
36 48 [5] no
R/PIO1_1/AD3
37 49 [5] no
PIO1_2/SWDIO/AD4 38 50 [5] no
www.PDIaOt1aS_h3e/AeDt45U/W.coAmKEUP 39 51 [6] no
PIO1_4/AD6
40 52 [5] no
I/O I; PU PIO0_27 — General purpose digital input/output pin
(high-current output driver).
O-
ACMP0_O — Output for comparator 0.
I/O I; PU PIO0_28 — General purpose digital input/output pin
(high-current output driver).
O-
ACMP1_O — Output for comparator 1.
I-
CT16B0_CAP0 — Capture input, channel 0 for 16-bit timer 0.
O-
CT16B0_MAT0 — Match output, channel 0 for 16-bit timer 0.
I/O I; PU PIO0_29 — General purpose digital input/output pin
(high-current output driver).
I/O -
ROSC — Relaxation oscillator for 555 timer applications.
I-
CT16B0_CAP1 — Capture input, channel 1 for 16-bit timer 0.
O-
CT16B0_MAT1 — Match output, channel 1 for 16-bit timer 0.
I I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O -
PIO0_30 — General purpose digital input/output pin.
I-
AD0 — A/D converter, input 0.
I I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O -
PIO0_31 — General purpose digital input/output pin.
I-
AD1 — A/D converter, input 1.
I/O Port 1 — Port 1 is a 32-bit I/O port with individual direction and
function controls for each bit. The operation of port 1 pins
depends on the function selected through the IOCONFIG
register block. Pins PIO1_7 through PIO1_31 are not available.
O I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O -
PIO1_0 — General purpose digital input/output pin.
I-
AD2 — A/D converter, input 2.
I I; PU R — Reserved. Configure for an alternate function in the
IOCONFIG block.
I/O -
PIO1_1 — General purpose digital input/output pin.
I-
AD3 — A/D converter, input 3.
I/O I; PU PIO1_2 — General purpose digital input/output pin.
I/O -
SWDIO — Serial wire debug input/output, alternate location.
I-
AD4 — A/D converter, input 4.
I/O I; PU PIO1_3 — General purpose digital input/output pin.
I-
AD5 — A/D converter, input 5.
I-
WAKEUP — Deep power-down mode wake-up pin.
I/O I; PU PIO1_4 — General purpose digital input/output pin.
I-
AD6 — A/D converter, input 6.
LPC122X
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 21 February 2011
© NXP B.V. 2011. All rights reserved.
11 of 60
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LPC1224.PDF ] | |
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