PDF BK2423 Data sheet ( Hoja de datos )

Número de pieza	BK2423
Descripción	Low Power High Performance 2.4 GHz GFSK Transceiver
Fabricantes	Beken
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BK2423 Low Power High Performance 2.4 GHz GFSK Transceiver Features 2400-2483.5 MHz ISM band operation Support 250Kbps, 1Mbps and 2 Mbps air data rate Programmable output power Low power consumption Tolerate +/- 60ppm 16 MHz crystal Variable payload length from 1 to 32bytes Automatic packet processing 6 data pipes for 1:6 star networks 1.9V to 3.6V power supply 4-pin SPI interface with maximum 8 MHz clock rate Compact 20-pin 3x3 or 4x4mm QFN package Applications Wireless PC peripherals Wireless mice and keyboards Wireless gamepads Wireless audio VOIP and wireless headsets Block Diagram Pin Assignments VSS CDVDD VDD VSS IREF 20 19 18 17 16 CE 1 CSN 2 SCK 3 MOSI 4 MISO 5 BK2423 15 VDD 14 VSS 13 RFN 12 RFP 11 VDDPA 6 7 8 9 10 IRQ VDD VSS XTALP XTALN Remote controls Consumer electronics Home automation Toys Personal health and entertainment RFP RFN Integrated TDD RF Transceiver FM Demodulator Power Management FM Modulator Data Slicer Gaussian shaping XTALP XTALN Rx FIFO Packet Processing & State Control Tx FIFO CSN SCK MOSI MISO IRQ CE Revision 2.0 May, 2011 Copyright © 2011 Beken Corporation Page 1 of 29 1 page BK2423 3 Pin Information VSS CDVDD VDD 20 19 18 VSS IREF 17 16 CE 1 CSN 2 SCK 3 MOSI 4 MISO 5 BK2423 15 VDD 14 VSS 13 RFN 12 RFP 11 VDDPA 6 7 8 9 10 IRQ VDD VSS XTALP XTALN Figure 2 BK2423 pin assignments (top view) for the QFN20 package PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name CE CSN SCK MOSI MISO IRQ VDD VSS XTALP XTALN VDDPA RFP RFN VSS VDD IREF VSS VDD CDVDD VSS Pin Function Description Digital Input Chip Enable Activates RX or TX mode Digital Input SPI Chip Select, Active low Digital Input SPI Clock Digital Input SPI Slave Data Input Digital Output SPI Slave Data Output with tri-state option Digital Output Maskable interrupt pin, Active low Power Power Supply (1.9 V to 3.6 V DC) Ground Ground (0 V) Analog Output Crystal oscillator, node P (inverter output) Analog Input Crystal oscillator, node N (inverter input) Power 1.8V Regulator output for PA,TX:1.8V,RX:0V RF port RF output (PA) /input (LNA), port P. RF port RF output (PA) /Input (LNA), port N. Ground Ground (0 V) Power Power Supply (1.9 V to 3.6 V DC) Analog Output Ground Reference current generation. A 22Kohm external resistor connected to ground. Ground (0 V) Power Power Supply (1.9 V to 3.6 V DC) Analog Output Digital regulator output decoupling capacitor Ground Ground (0 V) Table 1 BK2423 pin functions Revision 2.0 Proprietary and Confidential Page 5 of 29 5 Page IRQ to MCU. Two packet loss counters (ARC_CNT and PLOS_CNT) are incremented each time a packet is lost. The ARC_CNT counts the number of retransmissions for the current transaction. The PLOS_CNT counts the total number of retransmissions since the last channel change. ARC_CNT is reset by initiating a new transaction. PLOS_CNT is reset by writing to the RF_CH register. It is possible to use the information in the OBSERVE_TX register to make an overall assessment of the channel quality. The PTX device will retransmit if its RX FIFO is full but received ACK frame has payload. As an alternative for PTX device to auto retransmit it is possible to manually set the BK2423 to retransmit a packet a number of times. This is done by the REUSE_TX_PL command. When auto acknowledge is enabled, the PRX device will automatically check the NO_ACK field in received packet, and if NO_ACK=0, it will automatically send an acknowledge packet to PTX device. If EN_ACK_PAY is set, and the acknowledge packet can also include pending payload in TX FIFO. 6 Data and Control Interface 6.1 TX/RX FIFO The data FIFOs are used to store payload that is to be transmitted (TX FIFO) or payload that is received and ready to be clocked out (RX FIFO). The FIFO is accessible in both PTX mode and PRX mode. There are three levels 32 bytes FIFO for both TX and RX, supporting both acknowledge mode or no acknowledge mode with up to six pipes. TX three levels, 32 byte FIFO RX three levels, 32 byte FIFO Both FIFOs have a controller and are BK2423 accessible through the SPI by using dedicated SPI commands. A TX FIFO in PRX can store payload for ACK packets to three different PTX devices. If the TX FIFO contains more than one payload to a pipe, payloads are handled using the first in first out principle. The TX FIFO in a PRX is blocked if all pending payloads are addressed to pipes where the link to the PTX is lost. In this case, the MCU can flush the TX FIFO by using the FLUSH_TX command. The RX FIFO in PRX may contain payload from up to three different PTX devices. . A TX FIFO in PTX can have up to three payloads stored. The TX FIFO can be written to by three commands, W_TX_PAYLOAD and W_TX_PAYLOAD_NO_ACK in PTX mode and W_ACK_PAYLOAD in PRX mode. All three commands give access to the TX_PLD register. The RX FIFO can be read by the command R_RX_PAYLOAD in both PTX and PRX mode. This command gives access to the RX_PLD register. The payload in TX FIFO in a PTX is NOT removed if the MAX_RT IRQ is asserted. In the FIFO_STATUS register it is possible to read if the TX and RX FIFO are full or empty. The TX_REUSE bit is also available in the FIFO_STATUS register. TX_REUSE is set by the SPI command REUSE_TX_PL, and is reset by the SPI command: W_TX_PAYLOAD or FLUSH TX. 6.2 Interrupt In BK2423 there is an active low interrupt (IRQ) pin, which is activated when TX_DS IRQ, RX_DR IRQ or MAX_RT IRQ are set high by the state machine in the STATUS register. The IRQ pin resets when MCU writes '1' to the IRQ source bit in the STATUS register. The IRQ mask in the CONFIG Revision 2.0 Proprietary and Confidential Page 11 of 29 11 Page

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