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PDF RT8855 Data sheet ( Hoja de datos )
| Número de pieza | RT8855 | |
| Descripción | 4/3/2/1-Phase PWM Controller | |
| Fabricantes | Richtek | |
| Logotipo |  |
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RT8855
4/3/2/1-Phase PWM Controller for AMD AM2/AM2+ CPUs
General Description
The RT8855 is a 4/3/2/1-phase synchronous buck
controller with two integrated MOSFET drivers for CPU
power application and a single-phase buck with integrated
MOSFET driver for North-Bridge (NB) chipset.The RT8855
uses differential inductor DCR current sense to achieve
phase current balance and active voltage positioning. Other
features include adjustable operating frequency, power
good indication, external error-amp compensation, over
voltage protection, over current protection and enable/
shutdown for various applications. The RT8855 comes to
a small footprint with WQFN-48L 7x7 package.
Applications
z Desktop CPU Core Power
z Low Voltage, High Current DC/ DC Converter
Ordering Information
RT8855
Package Type
QW : WQFN-48L 7x7 (W-Type)
Operating Temperature Range
G : Green (Halogen Free with Commer-
cial Standard)
Note :
Richtek Green products are :
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.
Features
z 12V Power Supply Voltage
z 4/3/2/1-Phase Power Conversion for VCORE Power
z 3 Embedded MOSFET Drivers (2 for CPU and 1 for
NB)
z Internal Regulated 5V Output
z Support AMD AM2 6-bit Parallel and AM2+ 7-bit
Serial VID Tables
z Continuous Differential Inductor DCR Current Sense
z Adjustable Frequency (Typically at 300kHz)
z Selectable 1 or 2 Phase in Power-Saving (PS) Mode
z Phase-Interleaving for VCORE and NB Controller
z Power Good Indication
z Adjustable Over Current Protection
z Over Voltage Protection
z Small 48-Lead WQFN Package
z RoHS Compliant and Halogen Free
Pin Configurations
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
PWROK 1
RT 2
FBRTN 3
FBRTN_NB 4
FB_NB 5
COMP_NB 6
ISP_NB 7
ISN_NB 8
ADJ 9
OFS 10
COMP 11
FB 12
GND
36 BOOT_NB
35 BOOT1
34 UGATE1
33 PHASE1
32 LGATE1
31 VCC12
30 LGATE2
29 PHASE2
28 UGATE2
49 27 BOOT2
26 PWM3
25 PWM4
13 14 15 16 17 18 19 20 21 22 23 24
WQFN-48L 7x7
DS8855-00 July 2008
www.richtek.com
1
1 page  
RT8855
Functional Pin Description
Pin No.
Pin Name
Pin Function
1 PWROK
PWROK Input Signal.
2 RT
Connect this pin to GND by a resistor to adjust frequency.
3 FBRTN
Remote sense ground for CORE.
4 FBRTN_NB
Remote sense ground for NB.
5 FB_NB
Inverting input of error-amp for NB.
6 COMP_NB
Output of error-amp and input of PWM comparator for NB.
7 ISP_NB
Positive current sense pin of NB
8 ISN_NB
Negative current sense pin of NB
9 ADJ
Connect this pin to GND by a resistor to set load line of
VCORE.
10 OFS
11 COMP
12 FB
13 IMAX_NB
Connect this pin to GND/5VCC by a resistor to set no-load
offset voltage of VCORE.
Output of error-amp and input of PWM comparator of VCORE.
Inverting input of error-amp of VCORE.
Connect this pin to GND by a resistor to set OCP of NB.
14 IMAX
Connect this pin to GND by a resistor to set OCP of VCORE.
15, 17, 19, 21 ISN1, ISN2, ISN3, ISN4
Negative current sense pin of channel 1, 2, 3 and 4.
16, 18, 20, 22 ISP1, ISP2, ISP3, ISP4
Positive current sense pin of channel 1, 2, 3 and 4.
23 PS
Power Saving Mode Selection Pin.
24 VCC5
Output of internal 5V regulator for control circuits power supply.
Connect this pin to GND by a ceramic capacitor larger than 1uF.
25,26 PWM4, PWM3
PWM output for channel 4 and channel 3.
27, 35, 36 BOOT2, BOOT1, BOOT_NB
Bootstrap supply for channel 2 and channel 1 and NB.
28, 34, 37 UGATE2, UGATE1, UGATE_NB Upper gate driver for channel 2 and channel 1 and NB.
29, 33, 38 PHASE2, PHASE1, PHASE_NB Switching node of channel 2 and channel 1 and NB.
30, 32, 39 LGATE2, LGATE1, LGATE_NB Lower gate driver for channel 2 and channel 1 and NB.
31, 40 VCC12, VCC12_NB
IC power supply. Connect this pin to 12V.
41 VID0/VFIXEN
42 VID1/PVI
43 VID2/SVD
PVI Mode : Used as voltage identification input for DAC.
SVI Mode : Functions as VFIXEN selection input.
This pin selects PVI/SVI mode based on the state of this pin
prior to EN signal.
PVI Mode : Used as voltage identification input for DAC.
PVI Mode : Used as voltage identification input for DAC.
SVI Mode : Serial data input.
44 VID3/SVC
PVI Mode : Used as voltage identification input for DAC.
SVI Mode : Serial clock input.
45, 46 VID4, VID5
PVI Mode : Used as voltage identification input for DAC.
47 PGOOD
Power Good Indicator (open drain).
48 EN
Exposed pad
(49)
GND
Enable Input Signal.
Reference Ground for the IC. The exposed pad must be
soldered to a large PCB and connected to GND for maximum
power dissipation.
DS8855-00 July 2008
www.richtek.com
5
5 Page 
RT8855
Table 3. SVI Send Byte-Address and Data Phase
Description / Example
bits Description
Address Phase
6 : 4 Always 110b
3 Not Applicable, ignored.
2 Not Applicable, ignored.
CORE Section. (Note)
1 If set then the following data byte contains the
VID code for CORE Section.
NB Section. (Note)
0 If set then the following data byte contains the
VID code for NB Section.
Data Phase
7
PSI_L Flag (Active Low). When asserted, the
VR is allowed to enter Power-Saving Mode.
6 : 0 VID Code.
Note : Assertion in both bit 1 and 0 will address the VID
code to both CORE and NB simultaneously.
Example :
SVI Address
Bits [6 : 0]
1100_000
1100_001
1100_110
1100_100
1100_010
1100_111
Description
Should be ignored.
Set VID on VDDNB.
Set VID on VDD0 and VDD1.
Set VID on VDD1.
Set VID on VDD0 or VDD (uniplane).
Set VID on VDDNB, VDD0 and
VDD1.
PWROK De-assertion
PWROK stays low after EN signal is asserted, and the
controller regulates all the planes according to the Pre-
PWROK Metal VID.
PGOOD is de-asserted as long as Pre-PWROK Metal VID
voltage is out of the initial voltage specifications.
V_FIX Mode Function
Anytime the pin VID0/VFIXEN is pulled high, the controller
enters V-FIX mode. When in V_FIX mode, both VCORE
and NB section voltages are governed by the information
shown in Table 4. Regardless of the state of PWROK, the
device will work in SVI mode. SVC and SVD are considered
as static VID and the output voltage will be changed
according to their status. Dynamic SVC/SVD-change
management is provided in this condition. V_FIX mode is
intended for system debug only.
DS8855-00 July 2008
Table 4. V_FIX Mode and Pre-PWROK Metal VID
Output Voltage (V)
SVC
SVD Pre-PWROK
V_FIX Mode
Metal VID
00
1.1V
1.4V
01
1.0V
1.2V
10
0.9V
1.0V
11
0.8V
0.8V
Power Ready Detection
During start-up, RT8855 will detect VCC12, VCC5 and
EN signal. Figure 2 shows the power ready detection
circuit. When VCC12 > 9.6V and VCC5 > 4.6V, POR
(Power On Reset) will go high. POR is the internal signal
to indicate all input powers are ready to let RT8855 and
the companioned MOSFET drivers to work properly. When
POR = L, RT8855 will turn off both high side and low side
MOSFETs.
VCC12
9.6V
CMP
+
-
VCC5
EN
4.6V
CMP
+
-
POR
Chip Enable
Figure 2. Circuit for Power Ready Detection
Power-Up Sequencing
Figure 3 and 4 are the power-up sequencing diagram of
RT8855. Once power_on_reset is valid (POR = H), on the
rising edge of the EN signal, the RT8855 detects the VID1
pin and determine to operate either in SVI or PVI mode.
Figure3 shows the PVI-mode power sequence, the
controller stays in T1 state waiting for valid parallel VID
code sent by CPU. After receiving valid parallel VID code,
VCORE continues ramping up to the specified voltage
according to the VID code in T2 state. Figure 4 shows the
SVI-mode power sequence, the controller samples the
two serial VID pins, SVC and SVD. Then, the controller
stores this value as the boot VID that is the so-called
“Pre-PWROK Metal VID” in T1 state. After the processor
starts with boot VID voltages, PWROK is asserted and
the processor initializes the serial VID interface in T2 state.
The processor uses the serial VID interface to issue VID
commands to move the power planes from the boot VID
values to the dual power planes in T3 state.
www.richtek.com
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet RT8855.PDF ] | |
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