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PDF HCPL-0721 Data sheet ( Hoja de datos )
| Número de pieza | HCPL-0721 | |
| Descripción | CMOS Optocoupler | |
| Fabricantes | Avago | |
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HCPL-0720/7720/0721/7721
40 ns Propagation Delay, CMOS Optocoupler
Data Sheet
Lead (Pb) Free
RcoomHSpl6iafnutlly
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
Available in either an 8-pin DIP or SO-8 package style
respectively, the HCPL-772X or HCPL-072X optocouplers
utilize the latest CMOS IC technology to achieve out-
standing performance with very low power consump-
tion. The HCPL-772X/072X require only two bypass ca-
pacitors for complete CMOS compatability.
Basic building blocks of the HCPL-772X/072X are a CMOS
LED driver IC, a high speed LED and a CMOS detector
IC. A CMOS logic input signal controls the LED driver IC
which supplies current to the LED. The detector IC incor-
porates an integrated photodiode, a high-speed tran-
simpedance amplifier, and a voltage comparator with an
output driver.
Functional Diagram
• +5 V CMOS compatibility
• 20 ns maximum prop. delay skew
• High speed: 25 MBd
• 40 ns max. prop. delay
• 10 kV/µs minimum common mode rejection
• –40 to 85°C temperature range
• Safety and regulatory approvals
UL recognized
– 3750 Vrms for 1 min. per UL 1577
– 5000 Vrms for 1 min. per UL 1577
(for HCPL-772X option 020)
CSA component acceptance notice #5
IEC/EN/DIN EN 60747-5-2
– VIORM = 630 Vpeak for HCPL-772X option 060
– VIORM = 560 Vpeak for HCPL-072X option 060
**VDD1 1
VI 2
*3
GND1 4
LED1
SHIELD
8 VDD2**
7 NC*
IO
6 VO
5 GND2
(PTORSUITTIHVAETpALpOBlLGicEIaCt)ions
VI, INPUT
H
L
LED•1 DiVgOit,aOlUfiTePlUdTbus isolation: CC-Link, DeviceNet, Profi-
OFF bus, SDHS
ON
•
AC
plasLma
display
panel
level
shifting
• Multiplexed data transmission
• Computer peripheral interface
• Microprocessor system interface
* Pin 3 is the anode of the internal LED and must be left unconnected
for guaranteed data sheet performance. Pin 7 is not connected
internally.
** A 0.1 µF bypass capacitor must be connected between pins 1 and
4, and 5 and 8.
TRUTH TABLE
POSITIVE LOGIC
VI LED1 Vo OUTPUT
H OFF H
L ON L
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
1 page  
Solder Reflow Thermal Profile
300
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC. PEAK
TEMP.
245°C
200
160°C
150°C
140°C
100
2.5°C ± 0.5°C/SEC.
3°C + 1°C/–0.5°C
PREHEATING TIME
150°C, 90 + 30 SEC.
30
SEC.
30
SEC.
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
SOLDERING
TIME
200°C
50 SEC.
ROOM
TEMPERATURE
00
TIGHT
TYPICAL
LOOSE
50 100 150 200 250
TIME (SECONDS)
Note: Non-halide flux should be used.
Pb-Free IR Profile
Tp
TL
217 °C
260 +0/-5 °C
RAMP-UP
3 °C/SEC. MAX.
Tsmax 150 - 200 °C
Tsmin
ts
PREHEAT
60 to 180 SEC.
tp
tL
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
20-40 SEC.
RAMP-DOWN
6 °C/SEC. MAX.
60 to 150 SEC.
25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
Note: Non-halide flux should be used.
Regulatory Information
The HCPL-772X/072X have been approved by the following organizations:
UL
Recognized under UL 1577, component recognition program, File E55361.
CSA
Approved under CSA Component Acceptance Notice #5, File CA88324.
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884Teil 2):2003-01. (Option 060 only)
5 Page 
Application Information
Bypassing and PC Board Layout
The HCPL-772X/072X optocouplers are extremely easy
to use. No external interface circuitry is required because
the HCPL-772X/072X use high-speed CMOS IC technol-
ogy allowing CMOS logic to be connected directly to the
inputs and outputs.
As shown in Figure 10, the only external components
required for proper operation are two bypass capaci-
tors. Capacitor values should be between 0.01 µF and
0.1 µF. For each capacitor, the total lead length between
both ends of the capacitor and the power-supply pins
should not exceed 20 mm. Figure 11 illustrates the rec-
ommended printed circuit board layout for the HPCL-
772X/072X.
VDD1
VI
C1
1
2
NC 3
GND1
4
8
7 NC
C2
VDD2
6 VO
5 GND2
C1, C2 = 0.01 µF TO 0.1 µF
Figure 10. Recommended printed circuit board layout.
VDD1
VI
GND1
C1
HCPL-0710 fig 11
Figure 11. Recommended printed circuit board layout.
VDD2
C2
VO
GND2
C1, C2 = 0.01 µF TO 0.1 µF
Propagation Delay, Pulse-Width Distortion and Propagation Delay
Skew
HCPL-0710 fig 12
Propagation Delay is a figure of merit which describes
how quickly a logic signal propagates through a sys-
tem. The propagation delay from low to high (tPLH) is the
amount of time required for an input signal to propa-
gate to the output, causing the output to change from
low to high. Similarly, the propagation delay from high
to low (tPHL) is the amount of time required for the input
signal to propagate to the output, causing the output to
change from high to low. See Figure 12.
INPUT
VI
OUTPUT
VO
10%
tPLH
90%
Figure 12.
tPHL
50%
90%
10%
5 V CMOS
0V
VOH
2.5 V CMOS
VOL
11
HCPL-0710 fig 13
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet HCPL-0721.PDF ] | |
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