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PDF AT24MAC402 Data sheet ( Hoja de datos )
| Número de pieza | AT24MAC402 | |
| Descripción | 2-Kbit Serial EEPROM | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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AT24MAC402 and AT24MAC602
I2C-Compatible (2-wire) 2-Kbit Serial EEPROM with a
Factory-Programmed EUI-48™ or EUI-64™Address
Plus an Embedded Unique 128-bit Serial Number
2-Kbit (256 x 8)
Standard Serial EEPROM Features
DATASHEET
Low-voltage Operation
̶ 1.7V Minimum (VCC = 1.7V to 5.5V)
Internally Organized as 256 x 8 (2K)
I2C-compatible (2-wire) Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bi-directional Data Transfer Protocol
400kHz (1.7V) and 1MHz (2.5V, 5.0V) Compatibility
Write Protect Pin for Hardware Data Protection of the Entire Array
Permanent and Reversible Software Write Protection for the First-half of the
Array
̶ Software Procedure to Verify Write Protect Status
16-byte Page Write Modes
̶ Partial Page Writes Allowed
Self-timed Write Cycle (5ms max)
High-reliability
̶ Endurance: 1,000,000 Write Cycles
̶ Data Retention: 100 Years
Green Package Options (PB/Halide-free/RoHS Compliant)
̶ 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, and 5-lead SOT23
Die Sale Options: Wafer Form and Tape and Reel
Enhanced Features in the MAC Serial EEPROM Family
Factory-programmed EUI-48 or EUI-64 Compatible Address
̶ Permanently Locked, Read-only Value
̶ Stored in a Separate Memory Area
̶ Guaranteed Unique EUI Address
Custom Programming Services Available
̶ Manage and Program Customer’s IEEE Assigned OUI
Unique Factory-programmed 128-bit Serial Number
̶ Unique for all Atmel® AT24CS, AT93CS, and AT25S Series Serial EEPROMs
̶ Permanently Locked, Read-only Value
̶ Stored in a Separate Memory Area
Atmel-8807E-SEEPROM-AT24MAC402-602-Datasheet_012015
1 page  
5. Pin Description
Serial Clock (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative
edge clock data out of each device.
Serial Data (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or open collector devices.
Device Addresses (A0, A1, A2): The A0, A1, and A2 pins are device address inputs that are hard wired for the
AT24MAC402/602. As many as eight 2K devices may be addressed on a single bus system. Device addressing
is discussed in detail in Section 9., “Device Addressing” on page 13.
Write Protect (WP): The AT24MAC402/602 has a Write Protect pin that provides hardware data protection.
When the Write Protect pin is connected to ground (GND), normal Read/Write operations to the full array are
possible. When the Write Protect pin is connected to VCC, all write operations to the memory are inhibited, but
read operations are still possible. However, due to capacitive coupling that may appear during customer
applications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up
resistor, Atmel recommends using 10k or less. The write protection operation is summarized in Table 5-1
below.
5.1 Write Protection Modes
Table 5-1. Write Protection Modes
WP Pin Status
VCC
GND or Floating
Permanent Write Protect
Register
—
Not Programmed
GND or Floating
Programmed
GND or Floating
—
Reversible Write Protect
Register
—
Not Programmed
—
Programmed
Part of the Array Write
Protected
Full Array (2K)
Normal Read/Write
First-half of Array
First-half of Array
AT24MAC402/602 [DATASHEET]
Atmel-8807E-SEEPROM-AT24MAC402-602-Datasheet_012015
5
5 Page 
Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock
cycle.
Figure 8-3. Output Acknowledge
SCL 1
89
Data IN
Data OUT
Start
Acknowledge
Standby Mode: The AT24MAC402/602 features a low-power standby mode which is enabled upon
Power-up or
After the receipt of the Stop condition and the completion of any internal operations.
2-Wire Software Reset: After an interruption in protocol, power loss or system reset, any 2-wire part can be
reset by following these steps:
1. Create a Start condition (if possible).
2. Clock nine cycles.
3. Create another Start condition followed by Stop condition as shown below.
The device should be ready for the next communication after above steps have been completed. In the event
that the device is still non-responsive or remains active on the SDA bus, a power cycle must be used to reset
the device.
Figure 8-4. Software Reset
Dummy Clock Cycles
SCL 1 2 3
Start
Condition
SDA
89
Start
Condition
Stop
Condition
AT24MAC402/602 [DATASHEET]
Atmel-8807E-SEEPROM-AT24MAC402-602-Datasheet_012015
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT24MAC402.PDF ] | |
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