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PDF 74ALVC32PW Data sheet ( Hoja de datos )
| Número de pieza | 74ALVC32PW | |
| Descripción | Quad 2-input OR gate | |
| Fabricantes | NXP Semiconductors | |
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74ALVC32
Quad 2-input OR gate
Rev. 3 — 20 January 2014
Product data sheet
1. General description
The 74ALVC32 is a quad 2-input OR gate.
Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.
2. Features and benefits
Wide supply voltage range from 1.65 V to 3.6 V
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
Complies with JEDEC standards:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
74ALVC32D 40 C to +85 C SO14
plastic small outline package; 14 leads;
body width 3.9 mm
74ALVC32PW 40 C to +85 C
TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
74ALVC32BQ 40 C to +85 C
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
Version
SOT108-1
SOT402-1
SOT762-1
1 page  
NXP Semiconductors
74ALVC32
Quad 2-input OR gate
Table 6. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 40 C to +85 C
Min Typ[1] Max
ICC
ICC
supply current
additional supply current
VCC = 3.6 V; VI = VCC or GND;
IO = 0 A
per input pin; VCC = 3.0 V to 3.6 V;
VI = VCC 0.6 V; IO = 0 A
-
-
0.2 10
5 750
CI input capacitance
- 3.5 -
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C.
10. Dynamic characteristics
Unit
A
A
pF
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter
Conditions
tpd propagation delay
CPD power dissipation
capacitance
CP to Qn; see Figure 6
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
per gate; VI = GND to VCC; VCC = 3.3 V
[1] Typical values are measured at Tamb = 25 C
[2] tpd is the same as tPHL and tPLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CL VCC2 fo) = sum of the outputs
Tamb = 40 C to +85 C Unit
Min Typ[1] Max
[2]
1.0 2.8 4.7 ns
1.0 2.0 3.1 ns
1.0 2.2 2.9 ns
1.0 2.0 2.8 ns
[3] - 25 - pF
74ALVC32
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 20 January 2014
© NXP B.V. 2014. All rights reserved.
5 of 14
5 Page 
NXP Semiconductors
74ALVC32
Quad 2-input OR gate
13. Abbreviations
Table 10. Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74ALVC32 v.3
20140120
Product data sheet
-
74ALVC32 v.2
• The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
74ALVC32 v.2
20071210
Product data sheet
-
74ALVC32 v.1
74ALVC32 v.1
20021115
Product specification -
-
74ALVC32
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 20 January 2014
© NXP B.V. 2014. All rights reserved.
11 of 14
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| PDF Descargar | [ Datasheet 74ALVC32PW.PDF ] | |
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