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CY7C1034DV33 fiches techniques PDF

Cypress Semiconductor - 6-Mbit (256K x 24) Static RAM

Numéro de référence CY7C1034DV33
Description 6-Mbit (256K x 24) Static RAM
Fabricant Cypress Semiconductor 
Logo Cypress Semiconductor 





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CY7C1034DV33 fiche technique
CY7C1034DV33
6-Mbit (256K X 24) Static RAM
Features
High speed
tAA = 10 ns
Low active power
ICC = 175 mA at f = 100 MHz
Low CMOS standby power
ISB2 = 25 mA
Operating voltages of 3.3 ± 0.3 V
2.0 V data retention
Automatic power-down when deselected
Transistor-transistor logic (TTL) compatible inputs and outputs
Easy memory expansion with CE1, CE2, and CE3 features
Available in Pb-free standard 119-Ball PBGA
Functional Description
The CY7C1034DV33 is a high performance CMOS static RAM
organized as 256K words by 24 bits. This device has an
automatic power-down feature that significantly reduces power
consumption when deselected.
To write to the device, enable the chip (CE1 LOW, CE2 HIGH,
and CE3 LOW) while forcing the Write Enable (WE) input LOW.
To read from the device, enable the chip by taking CE1 LOW, CE2
HIGH, and CE3 LOW, while forcing the Output Enable (OE) LOW
and the Write Enable (WE) HIGH. See the Truth Table on page
7 for a complete description of Read and Write modes.
The 24 IO pins (IO0 to IO23) are placed in a high impedance state
when the device is deselected (CE1 HIGH, CE2 LOW, or CE3
HIGH) or when the output enable (OE) is HIGH during a write
operation. (CE1 LOW, CE2 HIGH, CE3 LOW, and WE LOW).
Logic Block Diagram
INPUT BUFFER
A(9:0)
256K x 24
ARRAY
IO0 – IO23
COLUMN
DECODER
A(17:10)
CONTROL LOGIC
CE1, CE2, CE3
WE
OE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-08351 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 29, 2011

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