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PDF CY7C1059DV33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1059DV33 | |
| Descripción | 8-Mbit (1M x 8) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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Features
■ High speed
❐ tAA = 10 ns
■ Low active power
❐ ICC = 110 mA at f = 100 MHz
■ Low CMOS standby power
❐ ISB2 = 20 mA
■ 2.0 V data retention
■ Automatic power down when deselected
■ TTL-compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in Pb-free 44-pin TSOP-II package
■ Offered in standard and high reliability (Q) grades
Logic Block Diagram
CY7C1059DV33
8-Mbit (1M × 8) Static RAM
Functional Description
The CY7C1059DV33 is a high performance CMOS Static RAM
organized as 1M words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and tri-state drivers. To write to the device,
take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data
on the eight I/O pins (I/O0 through I/O7) is then written into the
location specified on the address pins (A0 through A19).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the I/O pins.
The eight input or output pins (I/O0 through I/O7) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), or a write operation is in
progress (CE LOW and WE LOW).
The CY7C1059DV33 is available in 44-pin TSOP-II package with
center power and ground (revolutionary) pinout.
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CE
WE
OE
INPUT BUFFER
1M x 8
ARRAY
COLUMN DECODER
POWER
DOWN
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-00061 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 12, 2011
1 page  
AC Switching Characteristics
Over the Operating Range[5]
Parameter
Description
Read Cycle
tpower[6]
VCC(typical) to the first access
tRC Read cycle time
tAA Address to data valid
tOHA
Data hold from address change
tACE
CE LOW to data valid
tDOE
OE LOW to data valid
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to low-Z
OE HIGH to high-Z[7, 8]
CE LOW to low-Z[8]
CE HIGH to high-Z[7, 8]
tPU CE LOW to power-up
tPD CE HIGH to power-down
Write Cycle[9, 10]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
Data setup to write end
Data hold from write end
WE HIGH to low-Z[8]
WE LOW to high-Z[7, 8]
CY7C1059DV33
–10
Min Max
100 –
10 –
– 10
2.5 –
– 10
–5
0–
–5
3–
–5
0–
– 10
10 –
7–
7–
0–
0–
7–
5–
0–
3–
–5
–12
Min Max
100 –
12 –
– 12
2.5 –
– 12
–6
0–
–6
3–
–6
0–
– 12
12 –
8–
8–
0–
0–
8–
6–
0–
3–
–6
Unit
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V.
6. tPOWER is the minimum amount of time that the power supply must be at stable, typical VCC values until the first memory access can be performed.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of “AC Test Loads and Waveforms” on page 4. Transition is measured when
the outputs enter a high impedance state.
8. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
9. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either
of these signals can terminate the write. The input data setup and hold timing must refer to the leading edge of the signal that terminates the Write.
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 001-00061 Rev. *H
Page 5 of 11
5 Page 
CY7C1059DV33
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© Cypress Semiconductor Corporation, 2005-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-00061 Rev. *H
Revised September 12, 2011
All products and company names mentioned in this document may be the trademarks of their respective holders.
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| PDF Descargar | [ Datasheet CY7C1059DV33.PDF ] | |
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