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PDF SH66L12B Data sheet ( Hoja de datos )
| Número de pieza | SH66L12B | |
| Descripción | OTP 2K 4-bit Microcontroller | |
| Fabricantes | Sino Wealth | |
| Logotipo |  |
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SH66L12B
OTP 2K 4-bit Microcontroller with LCD Driver
Features
SH6610C-based single-chip 4-bit micro controller with
LCD driver
Mask ROM: 2K X 16 bits
RAM: 326 X 4 bits
- 36 System Control Register
- 256 Data Memory
- 34 LCD RAM
Operating Voltage: 1.2V - 1.7V(Typical 1.5V)
16 CMOS Bi-directional I/O pins
4 level subroutine nesting (including interrupts)
Two 8-bit Auto Re-Loaded Timer
Warm-Up Timer
Powerful Interrupt Sources:
- External Interrupt (Falling edge)
- Timer0 Interrupt
- Timer1 Interrupt
- PORTB & PORTC Interrupt (Falling Edge)
Oscillator (Code Option)
- Crystal Oscillator: 32.768kHz
- RC Oscillator: 131kHz
Instruction Cycle Time (4/fOSC)
- 4/32.768kHz (≈ 122µs) for 32.768kHz crystal
- 4/131kHz (≈ 31µs) for 131kHz RC
Two Low Power Operation Modes: HALT and STOP
Reset
- Built-in Power-on Reset (POR)
- Built-in Watchdog Timer (WDT) (Code Option)
LCD Driver(8 segment shared with PORTC/PORTD):
- 34 SEG X 4 COM (1/4 Duty, 1/3 Bias)
- 34 SEG X 3 COM (1/3 Duty, 1/2 Bias)
- 34 SEG X 2 COM (1/2 Duty, 1/2 Bias)
Built-in Pull-high Resistor for PORTA- PORTD
Built-in Alarm Generator(Code Option)
- 2kHz
- 4kHz
Built-in Electroluminescent Light (EL-Light) Driver
Built-in Voltage Doubler and Tripler Charge Pump
Circuit
Built-in Resistor To Frequency Converter (RFC)
Low Power Consumption
Bonding Option for Multi-code Software
Special HALT/STOP Mode
Available in CHIP FORM
General Description
SH66L12B is a single-chip micro-controller. This device integrated a SH6610C CPU core, RAM, ROM, timer, LCD driver, I/O
ports, EL-light driver, watch dog timer, resistor to frequency converter, voltage doubler and tripler charge pump circuit and alarm
generator. The SH66L12B is recommended for thermometer.
1 V1.0
1 page  
SH66L12B
Functional Description
1. CPU
The CPU contains the following function blocks: Program
Counter, Arithmetic Logic Unit (ALU), Carry Flag,
Accumulator, Table Branch Register, Data Pointer (INX,
DPH, DPM, and DPL), and the Stack.
1.1. PC (Program Counter)
The PC is used for ROM addressing consisting of 12-bit:
Page Register (PC11) and Ripple Carry Counter (PC10, PC9,
PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0).
The program counter is loaded with data corresponding to
each instruction. The unconditional jump instruction (JMP)
can be set at 1-bit page register for higher than 2K.
The program counter can address only 4K program ROM.
(Refer to the ROM description).
1.2. ALU and CY
The ALU performs arithmetic and logic operations. The ALU
provides the following functions:
Binary addition/subtraction (ADC, ADCM, ADD, ADDM,
SBC, SBCM, SUB, SUBM, ADI, ADIM, SBI, SBIM)
Decimal adjustments for addition/subtraction (DAA, DAS)
Logic operations (AND, ANDM, EOR, EORM, OR, ORM,
ANDIM, EORIM, ORIM)
Decisions (BA0, BA1, BA2, BA3, BAZ, BNZ, BC, BNC)
Logic Shift (SHR)
The Carry Flag (CY) holds the ALU overflow that the
arithmetic operation generates. During an interrupt service or
CALL instruction, the carry flag is pushed into the stack and
recovered from the stack by the RTNI instruction. It is
unaffected by the RTNW instruction.
1.3. Accumulator
The accumulator is a 4-bit register holding the results of the
arithmetic logic unit. In conjunction with the ALU, data is
transferred between the accumulator and system register, or
data memory can be performed.
1.4. Table Branch Register (TBR)
Table Data can be stored in program memory and can be
referenced by using Table Branch (TJMP) and Return
Constant (RTNW) instructions. The TBR and AC are placed
by an offset address in program ROM. TJMP instruction
branch into address ((PC11 - PC8) X (28) + (TBR, AC)). The
address is determined by RTNW to return look-up value into
(TBR, AC). ROM code bit7 - bit4 is placed into TBR and
Bit3-Bit0 into AC.
1.5. Data Pointer
The Data Pointer can indirectly address data memory.
Pointer address is located in register DPH (3-bit), DPM (3-bit)
and DPL (4-bit). The addressing range is 000H--3FFH.
Pseudo index address (INX) is used to read or write Data
memory, then RAM address Bit9-0 which comes from DPH,
DPM and DPL.
1.6. Stack
The stack is a group of registers used to save the contents of
CY & PC (11-0) sequentially with each subroutine call or
interrupt. The MSB is saved for CY and it is organized into 13
bits X 4 levels. The stack is operated on a first-in, last-out
basis and returned sequentially to the PC by the return
instructions (RTNI/RTNW).
Note:
The stack nesting includes both subroutine calls and
interrupts requests. The maximum allowed for subroutine
calls and interrupts are 4 levels. If the number of calls and
interrupt requests exceeds 4, then the bottom of stack will be
shifted out, that program execution may enter an abnormal
state.
2. RAM
Built-in RAM contains general-purpose data memory and system register. Because of its static nature, the RAM can keep data
after the CPU entering STOP or HALT.
2.1 RAM Addressing
Data memory and system register can be accessed in one instruction by direct addressing. The following is the memory
allocation map:
System register: $000 - $01F, $340 - $343
Data memory: $020 - $11F (256 X 4 bits, divided into 2 banks)
LCD RAM space: $300 - $321 (34 X 4 bits)
RAM Bank Table:
Bank 0
B=0
Bank 1
B=1
Bank 2
B=2
Bank 6
B=6
$000 - $07F $080 - $0FF $100 - $17F $300 - $37F
Where, B: RAM bank bit use in instructions
5
5 Page 
7. Timer
SH66L12B has two 8-bit timers.
The timer/counter has the following features:
- 8-bit up-counting timer/counter.
- Automatic re-load counter.
- 8-level prescaler.
- Interrupt on overflow from $FF to $00.
The following is a simplified timer block diagram.
tOSC
SYNC
System
clock
Prescaler
8-BIT
COUNTER
TM.2 TM.1 TM.0
The timers provide the following functions:
- Programmable interval timer function.
- Read counter value.
7.1. Timer0 and Timer1 Configuration and Operation
Both Timer0 and Timer1 consist of an 8-bit write-only timer
load register (TL0L, TL0H; TL1L, TL1H), and an 8-bit
read-only timer counter (TC0L, TC0H; TC1L, TC1H). Each of
them has low order digits and high order digits. The timer
counter can be initialized by writing data into the timer load
register (TL0L, TL0H; TL1L, TL1H).
SH66L12B
The low-order digit should be written first, and then the
high-order digit. The timer counter is automatically loaded
with the contents of the load register when the high order
digit is written or counter counts overflow from $FF to $00.
Timer Load Register: Since the register H controls the
physical READ and WRITE operations.
Please follow these steps:
Write Operation:
Low nibble first
High nibble to update the counter
Read Operation:
High nibble first
Low nibble followed.
Load Reg. L Load Reg. H
8-bit timer counter
Latch Reg. L
7.2. Timer0 and Timer1 mode register
The timer can be programmed in several different prescaler ratios by setting the Timer Mode register (TM0, TM1). The 8-bit
counter counts prescaler overflow output pulses. The Timer Mode registers (TM0, TM1) are 4-bit registers used for the timer
control as shown in table1 and table 2. These mode registers select the input pulse sources into the timer.
Table 1: Timer0 Mode Register $02:
Table 2: Timer1 Mode Register $03:
TM0.2
0
0
0
0
1
1
1
1
TM0.1
0
0
1
1
0
0
1
1
TM0.0
0
1
0
1
0
1
0
1
Prescaler
Divide Ratio
/211
/29
/27
/25
/23
/22
/21
/20
Clock Source
fOSC/4
fOSC/4
fOSC/4
fOSC/4
fOSC/4
fOSC/4
fOSC/4
fOSC/4
TM1.2
0
0
0
0
1
1
1
1
TM1.1
0
0
1
1
0
0
1
1
TM1.0
0
1
0
1
0
1
0
1
Prescaler
Divide Ratio
/211
/29
/27
/25
/23
/22
/21
/20
Clock Source
fOSC/4
fOSC/4
fOSC/4
fOSC/4
fOSC/4
fOSC/4
fOSC/4
fOSC/4
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SH66L12B.PDF ] | |
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