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PDF NB3N121K Data sheet ( Hoja de datos )
| Número de pieza | NB3N121K | |
| Descripción | 3.3V Differential 1:21 Fanout Clock and Data Driver | |
| Fabricantes | ON Semiconductor | |
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NB3N121K
3.3V Differential 1:21
Fanout Clock and Data
Driver with HCSL Outputs
Description
The NB3N121K is a differential 1:21 Clock and Data fanout buffer
with High−speed Current Steering Logic (HCSL) outputs optimized
for ultra low propagation delay variation. The NB3N121K is designed
with HCSL PCI Express clock distribution and FBDIMM applications
in mind.
Inputs can directly accept differential LVPECL, HCSL, and LVDS
signals per Figures 7, 8, and 9. Single ended LVPECL, HCSL,
LVCMOS, or LVTTL levels are accepted with a proper external Vth
reference supply per Figures 4 and 10. Input pins incorporate separate
internal 50 W termination resistors allowing additional single ended
system interconnect flexibility.
Output drive current is set by connecting a 475 W resistor from
IREF (Pin 1) to GND per Figure 6. Outputs can also interface to
LVDS receivers when terminated per Figure 11.
The NB3N121K specifically guarantees low output–to–output
skew. Optimal design, layout, and processing minimize skew within a
device and from device to device. System designers can take
advantage of the NB3N121K’s performance to distribute low skew
clocks across the backplane or the motherboard.
Features
• Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and
400 MHz
• 340 ps Typical Rise and Fall Times
• 800 ps Typical Propagation Delay
• 100 ps Max Within Device Skew
• 150 ps Max Device−to−Device Skew
• Dtpd 100 ps Maximum Propagation Delay Variation Per Each
Differential Pair
• 0.1 ps Typical RMS Additive Phase Jitter
• LVDS Output Levels Optional with Interface Termination
• Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
• Typical HCSL Output Level (700 mV Peak−to−Peak)
• These are Pb−Free Devices
Applications
• Clock Distribution
• PCIe I, II, III
• Networking
• High End Computing
• Routers
End Products
• Servers
• FBDIMM Memory Card
© Semiconductor Components Industries, LLC, 2012
March, 2012 − Rev. 1
1
http://onsemi.com
1 52
QFN−52
MN SUFFIX
CASE 485M
MARKING DIAGRAM*
52
1
NB3N
121K
AWLYYWWG
A = Assembly Site
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
Q0
VTCLK
Q0
Q1
Q1
CLK
CLK Q19
VTCLK
VCC
GND
IREF
RREF
Q19
Q20
Q20
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Publication Order Number:
NB3N121K/D
1 page  
NB3N121K
Table 4. DC CHARACTERISTICS (VCC = 3.0 V to 3.6 V, TA = −40°C to +85°C Note 5)
Symbol
Characteristic
Min Typ Max Unit
IGND GND Supply Current (All Outputs Loaded)
ICC Power Supply Current (All Outputs Loaded)
IIH Input HIGH Current
IIL Input LOW Current
RTIN Internal Input Termination Resistor
DIFFERENTIAL INPUT DRIVEN SINGLE*ENDED (See Figures 4 and 5)
−150
45
120
440
2.0
−2.0
50
150
500
150
55
mA
mA
mA
mA
W
Vth Input Threshold Reference Voltage Range (Note 6)
VIH Single−Ended Input HIGH Voltage
VIL Single−Ended Input LOW Voltage
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7, 8 and 9)
350
Vth + 150
GND
VCC − 1000
VCC
Vth − 150
mV
mV
mV
VIHD Differential Input HIGH Voltage
VILD Differential Input LOW Voltage
VID Differential Input Voltage (VIHD − VILD)
VCMR Input Common Mode Range
HCSL OUTPUTS (Figure 4)
425
GND
150
350
VCC − 850
VCC − 1000
VCC − 850
VCC − 1000
mV
mV
mV
mV
VOH Output HIGH Voltage
600 740 900 mV
VOL Output LOW Voltage
−150
0
150 mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Measurements taken with with outputs loaded 50 W to GND. Connect a 475 W resister from IREF (Pin 1) to GND. See Figure 6.
6. Vth is applied to the complementary input when operating in single ended mode per Figure 4.
http://onsemi.com
5
5 Page 
NB3N121K
PACKAGE DIMENSIONS
QFN52 8x8, 0.5P
CASE 485M−01
ISSUE C
D
ÉÉÉÉPIN ONE
ÉÉÉÉÉÉÉÉÉÉÉÉREFERENCE
A
B
E
2X
0.15 C
2X
0.15 C
0.10 C
0.08 C
SEATING PLANE
A1
52 X L
14
13
A2
A3 REF
D2
26
27
A
C
E2
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30
MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MILLIMETERS
DIM MIN MAX
A 0.80 1.00
A1 0.00 0.05
A2 0.60 0.80
A3 0.20 REF
b 0.18 0.30
D 8.00 BSC
D2 6.50 6.80
E 8.00 BSC
E2 6.50 6.80
e 0.50 BSC
K 0.20 ---
L 0.30 0.50
RECOMMENDED
SOLDERING FOOTPRINT
8.30
6.75
52X
0.62
6.75 8.30
52 X K
1
52
e
39
40
52 X b NOTE 3
0.10 C A B
PKG
OUTLINE
0.50
PITCH
52X
0.30
DIMENSIONS: MILLIMETERS
0.05 C
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
http://onsemi.com
11
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NB3N121K/D
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet NB3N121K.PDF ] | |
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