|
|
PDF NB3N1900K Data sheet ( Hoja de datos )
| Número de pieza | NB3N1900K | |
| Descripción | 3.3V 100/133MHz Differential 1:19 HCSL Clock ZDB/Fanout Buffer | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de NB3N1900K (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
|
No Preview Available !
NB3N1900K
3.3V 100/133 MHz
Differential 1:19 HCSL
Clock ZDB/Fanout Buffer for
PCIe[
Description
The NB3N1900K differential clock buffers are designed to work in
conjunction with a PCIe compliant source clock synthesizer to provide
point−to−point clocks to multiple agents. The device is capable of
distributing the reference clocks for Intel® QuickPath Interconnect
(Intel QPI), PCIe Gen1, Gen2, Gen3. The NB3N1900K internal PLL is
optimized to support 100 MHz and 133 MHz frequency operation.
The NB3N1900K supports HCSL output levels.
Features
• Fixed Feedback Path for Lowest Input−to−Output Delay
• Eight Dedicated OE# Pins for Hardware Control of Outputs
• PLL Bypass Configurable for PLL or Fanout Operation
• Selectable PLL Bandwidth
• Spread Spectrum Compatible: Tracks Input Clock Spreading for Low
EMI
• SMBus Programmable Configurations
• 100 MHz and 133 MHz PLL Mode to Meet the Next Generation
PCIe Gen2 / Gen 3 and Intel QPI Phase Jitter
• 2 Tri−Level Addresses Selection (Nine SMBUS Addresses)
• Cycle−to−Cycle Jitter: < 50 ps
• Output−to−Output Skew: < 65 ps
• Input−to−Output Delay: Fixed at 0 ps
• Input−to−Output Delay Variation: < 50 ps
• Phase Jitter: PCIe Gen3 < 1 ps rms
• Phase Jitter: QPI 9.6GB/s < 0.2 ps rms
• QFN 72−pin Package, 10 mm x 10 mm
• These are Pb−Free Devices
www.onsemi.com
MARKING
DIAGRAM*
1 72
QFN72
MN SUFFIX
CASE 485DK
1
NB3N
1900K
AWLYYWWG
NB3N1900K = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 20 of
this data sheet.
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 4
1
Publication Order Number:
NB3N1900K/D
1 page  
Table 7. PIN DESCRIPTION
Pin #
Pin Name
1 VDDA
2 GNDA
3 IREF
4 100M_133M#
5 HBW_BYP_LBW#
6 PWRGD/PWRDN#
7 GND
8 VDDR
9 CLK_IN
10 CLK_IN#
11 SA_0
12 SDA
13 SCL
14 SA_1
15 NC
16 NC
17 FB_OUT#
18 FB_OUT
19 DIF0
20 DIF0#
21 VDD
22 DIF1
23 DIF1#
24 DIF2
25 DIF2#
26 GND
27 DIF3
28 DIF3#
29 DIF4
30 DIF4#
31 VDD
32 DIF5
33 DIF5#
34 OE5#
35 DIF6
36 DIF6#
37 OE6#
NB3N1900K
Pin Type
Description
PWR 3.3 V power for the PLL core.
PWR Ground pin for the PLL core.
OUT
This pin establishes the reference for the differential current−mode output pairs. It
requires a fixed precision resistor to ground. 475 W is the standard value for 100 W
differential impedance. Other impedances require different values.
See data sheet.
IN
Input to select operating frequency
1 = 100.00 MHz, 0 = 133.33 MHz
IN
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for Details.
IN
Notifies device to sample latched inputs and start up on first high assertion, or exit
Power Down Mode on subsequent assertions. Low enters Power Down Mode.
PWR Ground pin.
PWR
3.3 V power for differential input clock (receiver). This VDD should be treated as an
analog power rail and filtered appropriately.
IN 0.7 V Differential true input
IN 0.7 V Differential complementary Input
IN
SMBus address bit. This is a tri−level input that works in conjunction with the SA_1
to decode 1 of 9 SMBus Addresses.
I/O Data pin of SMBus circuitry, 5V tolerant
IN Clock pin of SMBus circuitry, 5V tolerant
IN
SMBus address bit. This is a tri−level input that works in conjunction with the SA_0
to decode 1 of 9 SMBus Addresses.
N/A No Connection.
N/A No Connection.
OUT
Complementary half of differential feedback output, provides feedback signal to the
PLL for synchronization with input clock to eliminate phase error.
OUT
True half of differential feedback output, provides feedback signal to the PLL for
synchronization with the input clock to eliminate phase error.
OUT 0.7 V differential true clock output
OUT 0.7 V differential complementary clock output
PWR Power supply, nominal 3.3 V
OUT 0.7 V differential true clock output
OUT 0.7 V differential complementary clock output
OUT 0.7 V differential true clock output
OUT 0.7 V differential complementary clock output
PWR Ground pin.
OUT 0.7 V differential true clock output
OUT 0.7 V differential complementary clock output
OUT 0.7 V differential true clock output
OUT 0.7 V differential complementary clock output
PWR Power supply, nominal 3.3 V
OUT 0.7 V differential true clock output
OUT 0.7 V differential complementary clock output
IN
Active low input for enabling DIF pair 5.
1 = disable outputs, 0 = enable outputs
OUT 0.7 V differential true clock output
OUT 0.7 V differential complementary clock output
IN
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
www.onsemi.com
5
5 Page 
NB3N1900K
Table 14. ELECTRICAL CHARACTERISTICS − PHASE JITTER PARAMETERS
(VDD = VDDA = 3.3 V ±5%, TA = −10°C to +70°C), See Test Loads for Loading Conditions.
Symbol
Parameter
Conditions (Notes 31 and 36)
Min Typ Max Unit
tjphPCIeG1
tjphPCIeG2
PCIe Gen 1 (Notes 32 and 33)
PCIe Gen 2 Lo Band
10 kHz < f < 1.5 MHz (Note 32)
PCIe Gen 2 High Band
1.5 MHz < f < Nyquist (50 MHz)
(Note 32)
36 86 ps (p−p)
3
ps
(rms)
3.1
ps
(rms)
tjphPCIeG3 Jitter, Phase
PCIe Gen 3
(PLL BW of 2−4 MHz, CDR = 10 MHz)
(Note 32)
1
ps
(rms)
QPI & SMI
(100.00 MHz or 133.33 MHz,
4.8 Gb/s, 6.4 Gb/s 12UI) (Note 34)
0.5
ps
(rms)
tjphQPI_SMI
QPI & SMI
(100.00 MHz, 8.0 Gb/s, 12UI) (Note 34)
0.3
ps
(rms)
QPI & SMI
(100.00 MHz, 9.6 Gb/s, 12UI) (Note 34)
0.2
ps
(rms)
tjphPCIeG1
tjphPCIeG2
PCIe Gen 1 (Notes 32 and 33)
PCIe Gen 2 Lo Band
10 kHz < f < 1.5 MHz (Notes 32 and 35)
PCIe Gen 2 High Band
1.5 MHz < f < Nyquist (50 MHz)
(Notes 32 and 35)
10 ps (p−p)
0.3
ps
(rms)
0.7
ps
(rms)
tjphPCIeG3 Additive Phase Jitter, Bypass
mode
PCIe Gen 3
(PLL BW of 2−4 MHz, CDR = 10 MHz)
(Notes 32 and 35)
0.3
ps
(rms)
QPI & SMI
(100.00 MHz or 133.33 MHz, 4.8 Gb/s,
6.4 Gb/s 12UI) (Notes 34 and 35)
0.3
ps
(rms)
tjphQPI_SMI
QPI & SMI
(100.00 MHz, 8.0 Gb/s, 12UI) (Notes 34 and 35)
0.1
ps
(rms)
QPI & SMI
(100.00 MHz, 9.6 Gb/s, 12UI) (Notes 34 and 35)
0.1
ps
(rms)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
31. Applies to all outputs.
32. See http://www.pcisig.com for complete specs
33. Sample size of at least 100K cycles. This figures extrapolates to 108 ps pk−pk @ 1M cycles for a BER of 1−12.
34. Calculated from Intel−supplied Clock Jitter Tool v 1.6.3.
35. For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)2 = (total jitter)2 - (input jitter)2
36. Guaranteed by design and characterization, not tested in production
www.onsemi.com
11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet NB3N1900K.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| NB3N1900K | 3.3V 100/133MHz Differential 1:19 HCSL Clock ZDB/Fanout Buffer | ON Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |