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PDF ATWILC1000A Data sheet ( Hoja de datos )
| Número de pieza | ATWILC1000A | |
| Descripción | IEEE 802.11 b/g/n Link Controller SoC | |
| Fabricantes | ATMEL Corporation | |
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ATWILC1000A-MUT
IEEE 802.11 b/g/n Link Controller SoC
Datasheet
Description
ATWILC1000A is a single chip IEEE® 802.11 b/g/n Radio/Baseband/MAC link
controller optimized for low-power mobile applications. ATWILC1000A supports
single stream 1x1 802.11n mode providing up to 72Mbps PHY rate. The
ATWILC1000A features fully integrated Power Amplifier, LNA, Switch, and Power
Management. Implemented in 65nm CMOS technology, the ATWILC1000A
offers very low power consumption while simultaneously providing high
performance and minimal bill of materials.
The ATWILC1000A supports two and three Bluetooth coexistence protocols. The
ATWILC1000A provides multiple peripheral interfaces including UART, SPI, I2C,
and SDIO. The only external clock source needed for the ATWILC1000A is a
high-speed crystal or oscillator with a wide range of reference clock frequencies
supported (12-40MHz). The ATWILC1000A is available in both QFN and Wafer
Level Chip Scale Package (WLCSP) packaging.
Features
IEEE 802.1 b/g/n 20MHz (1x1) solution
Single spatial stream in 2.4GHz ISM band
Integrated PA and T/R Switch
Superior Sensitivity and Range via advanced PHY signal processing
Advanced Equalization and Channel Estimation
Advanced Carrier and Timing Synchronization
Wi-Fi Direct and Soft-AP support
Supports IEEE 802.11 WEP, WPA, WPA2 Security
Supports China WAPI security
Superior MAC throughput via hardware accelerated two-level A-MSDU/A-
MPDU frame aggregation and block acknowledgement
On-chip memory management engine to reduce host load
SPI, SDIO, UART, and I2C host interfaces
2/3 wire Bluetooth coexistence interface
Operating temperature range of -40°C to +85°C
Power save modes:
– <1µA Deep Power Down mode typical @3.3V I/O
– 280µA Doze mode with chip settings preserved (used for beacon monitoring)
– On-chip low power sleep oscillator
– Fast host wake-up from Doze mode by a pin or host I/O transaction
Atmel-42351C-ATWILC1000A-MUT-SmartConnect-Datasheet_022015
1 page  
Figure 3-1. Pin Assignment
Table 3-1. Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Pin Name
Pin Type
TP_P
Analog
VDD_RF_RX
Power
VDD_AMS
Power
VDD_RF_TX
Power
VDD_BATT_PPA
Power
VDD_BATT_PA
Power
RFIOP
Analog
RFION
Analog
SDIO_SPI_CFG
Digital Input
GPIO0/HOST_WAKE Digital I/O, Programmable Pull-Up
GPIO2/IRQN
Digital I/O, Programmable Pull-Up
SD_DAT3
Digital I/O, Programmable Pull-Up
SD_DAT2/SPI_RXD Digital I/O, Programmable Pull-Up
VDDC
Power
VDDIO
Power
SD_DAT1/SPI_SSN Digital I/O, Programmable Pull-Up
SD_DAT0/SPI_TXD Digital I/O, Programmable Pull-Up
SD_CMD/SPI_SCK Digital I/O, Programmable Pull-Up
SD_CLK
Digital I/O, Programmable Pull-Up
Description
Test Pin/Customer No Connect
Tuner RF Supply (see Section 9.1 and Table 9-3)
Tuner BB Supply (see Section 9.1 and Table 9-3)
Tuner RF Supply (see Section 9.1 and Table 9-3)
PA 1st Stage Supply (see Section 9.1 and Table 9-3)
PA 2nd Stage Supply (see Section 9.1 and Table 9-3)
Pos RF Differential I/O (see Table 9-3)
Neg RF Differential I/O (see Table 9-3)
Tie to 1 for SPI, 0 for SDIO
GPIO0/SLEEP Mode Control
GPIO2/Device Interrupt
SDIO Data3
SDIO Data2/SPI Data Rx
Digital Core Power Supply (see Section 9.1 and Table 9-3)
Digital I/O Power Supply (see Section 9.1 and Table 9-3)
SDIO Data1/SPI Slave Select
SDIO Data0/SPI Data Tx
SDIO Command/SPI Clock
SDIO Clock
ATWILC1000A-MUT [DATASHEET]
Atmel-42351C-ATWILC1000A-MUT-SmartConnect-Datasheet_022015
55
5 Page 
6.2 Memory Subsystem
The APS3 core uses a 128KB instruction/boot ROM along with a 128KB instruction RAM and a 64KB data
RAM. In addition, the device uses a 128KB shared RAM, accessible by the processor and MAC, which allows
the APS3 core to perform various data management tasks on the TX and RX data packets.
6.3 Non-Volatile Memory (EFuse)
ATWILC1000A has 768 bits of non-volatile EFuse memory that can be read by the CPU after device reset.
This non-volatile one-time-programmable (OTP) memory can be used to store customer-specific parameters,
such as MAC address; various calibration information, such as TX power, crystal frequency offset, etc; and
other software-specific configuration parameters. The EFuse is partitioned into six 128-bit banks. Each bank
has the same bit map, which is shown in Figure 6-1. The purpose of the first 80 bits in each bank is fixed, and
the remaining 48 bits are general-purpose software dependent bits, or reserved for future use. Since each
bank can be programmed independently, this allows for several updates of the device parameters following the
initial programming, e.g. updating MAC address. Refer to ATWILC1000A Programming Guide for the EFuse
programming instructions.
Figure 6-1. EFuse Bit Map
11
3
4
1
1
7
1 15
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Flags
8
F
48
MAC ADDR
8 16
G FO
128 Bits
7 WLAN Subsystem
The WLAN subsystem is composed of the Media Access Controller (MAC) and the Physical Layer (PHY). The
following two subsections describe the MAC and PHY in detail.
ATWILC1000A-MUT [DATASHEET]
Atmel-42351C-ATWILC1000A-MUT-SmartConnect-Datasheet_022015
11 1
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