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TC58BVG0S3HTAI0 fiches techniques PDF

Toshiba - 1 GBIT (128M x 8-BIT) CMOS NAND E2PROM

Numéro de référence TC58BVG0S3HTAI0
Description 1 GBIT (128M x 8-BIT) CMOS NAND E2PROM
Fabricant Toshiba 
Logo Toshiba 





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TC58BVG0S3HTAI0 fiche technique
TC58BVG0S3HTAI0
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
1 GBIT (128M × 8 BIT) CMOS NAND E2PROM
DESCRIPTION
The TC58BVG0S3HTAI0 is a single 3.3V 1 Gbit (1,107,296,256 bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 64 pages × 1024blocks.
The device has a 2112-byte static register which allows program and read data to be transferred between the
register and the memory cell array in 2112-bytes increments. The Erase operation is implemented in a single block
unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages).
The TC58BVG0S3HTAI0 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
The TC58BVG0S3HTAI0 has ECC logic on the chip and 8bit read errors for each 528Bytes can be corrected
internally.
FEATURES
Organization
x8
Memory cell array 2112 × 64K × 8
Register
2112× 8
Page size
2112 bytes
Block size
(128K + 4K) bytes
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
ECC Status Read
Mode control
Serial input/output
Command control
Number of valid blocks
Min 1004 blocks
Max 1024 blocks
Power supply
VCC = 2.7V to 3.6V
Access time
Cell array to register 40 µs typ.
Serial Read Cycle
25 ns min (CL=50pF)
Program/Erase time
Auto Page Program
Auto Block Erase
330 µs/page typ.
2.5 ms/block typ.
Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
30 mA max.
30 mA max
30 mA max
50 µA max
Package
TSOP I 48-P-1220-0.50 (Weight: 0.53 g typ.)
8bit ECC for each 528Bytes is implemented on a chip.
1 2012-08-31C

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