PDF AT32UC3C0128C Data sheet ( Hoja de datos )

Número de pieza	AT32UC3C0128C
Descripción	32-bit AVR Microcontroller
Fabricantes	ATMEL Corporation
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Features • High Performance, Low Power 32-bit AVR® Microcontroller – Compact Single-cycle RISC Instruction Set Including DSP Instruction Set – Built-in Floating-Point Processing Unit (FPU) – Read-Modify-Write Instructions and Atomic Bit Manipulation – Performing 1.49 DMIPS / MHz • Up to 91 DMIPS Running at 66 MHz from Flash (1 Wait-State) • Up to 49 DMIPS Running at 33 MHz from Flash (0 Wait-State) – Memory Protection Unit • Multi-hierarchy Bus System – High-Performance Data Transfers on Separate Buses for Increased Performance – 16 Peripheral DMA Channels Improves Speed for Peripheral Communication • Internal High-Speed Flash – 512 Kbytes, 256 Kbytes, 128 Kbytes, 64 Kbytes Versions – Single Cycle Access up to 33 MHz – FlashVault™ Technology Allows Pre-programmed Secure Library Support for End User Applications – Prefetch Buffer Optimizing Instruction Execution at Maximum Speed – 100,000 Write Cycles, 15-year Data Retention Capability – Flash Security Locks and User Defined Configuration Area • Internal High-Speed SRAM, Single-Cycle Access at Full Speed – 64 Kbytes (512 KB and 256 KB Flash), 32 Kbytes (128 KB Flash), 16 Kbytes (64 KB Flash) – 4 Kbytes on the Multi-Layer Bus System (HSB RAM) • External Memory Interface on AT32UC3C0 Derivatives – SDRAM / SRAM Compatible Memory Bus (16-bit Data and 24-bit Address Buses) • Interrupt Controller – Autovectored Low Latency Interrupt Service with Programmable Priority • System Functions – Power and Clock Manager – Internal 115KHz (RCSYS) and 8MHz/1MHz (RC8M) RC Oscillators – One 32 KHz and Two Multipurpose Oscillators – Clock Failure detection – Two Phase-Lock-Loop (PLL) allowing Independent CPU Frequency from USB or CAN Frequency • Windowed Watchdog Timer (WDT) • Asynchronous Timer (AST) with Real-Time Clock Capability – Counter or Calendar Mode Supported • Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency • Ethernet MAC 10/100 Mbps interface – 802.3 Ethernet Media Access Controller – Supports Media Independent Interface (MII) and Reduced MII (RMII) • Universal Serial Bus (USB) – Device 2.0 and Embedded Host Low Speed and Full Speed – Flexible End-Point Configuration and Management with Dedicated DMA Channels – On-chip Transceivers Including Pull-Ups • One 2-channel Controller Area Network (CAN) – CAN2A and CAN2B protocol compliant, with high-level mailbox system – Two independent channels, 16 Message Objects per Channel 32-bit AVR® Microcontroller AT32UC3C0512C AT32UC3C0256C AT32UC3C0128C AT32UC3C064C AT32UC3C1512C AT32UC3C1256C AT32UC3C1128C AT32UC3C164C AT32UC3C2512C AT32UC3C2256C AT32UC3C2128C AT32UC3C264C 32117D–AVR–01/12 1 page AT32UC3C 2. Overview 2.1 Block diagram Figure 2-1. Block diagram RESET_N aWire TDO TCK TDI TMS VBUS D+ D- ID VBOF JTAG INTERFACE MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N USB INTERFACE 512/ 256/ 128/64 KB Flash Flash Controller 4 KB HSB RAM RXLINE[0] TXLINE[0] RXLINE[1] TXCAN[1] CANIF NEXUS CLASS 2+ OCD AVR32UC CPU MEMORY PROTECTION UNIT INSTR DATA INTERFACE INTERFACE LOCAL BUS INTERFACE 64/32/16 KB SRAM MM S S M S PBB M MS S HIGH SPEED BUS MATRIX M M MS CONFIGURATION REGISTERS BUS SM HSB HSB-PB BRIDGE C PB PERIPHERAL DMA CONTROLLER HSB HSB-PB BRIDGE A PB HSB PB HSB-PB BRIDGE B LOCAL BUS DATA[15..0] ADDR[23..0] NCS[3..0] NRD NWAIT NWE0 NWE1 RAS CAS SDA10 SDCK SDCKE SDWE W Memory R DMA DMA ETHERNET MAC COL, CRS, RXD[3..0], RX_CLK, RX_DV, RX_ER, TX_CLK MDC, TXD[3..0], TX_EN, TX_ER, SPEED MDIO DSR, DTR, DCD, RI RTS, CTS CLK USART1 PA TXD PB RXD PC PD RTS, CTS CLK TXD USART4 RXD supplied by VDDANA ADCREF0/1 ADCIN[15..0] ADCVREFP/N ANALOG TO DIGITAL CONVERTER 0/1 PERIPHERAL EVENT CONTROLLER USART0 USART2 USART3 SERIAL PERIPHERAL INTERFACE 1 PAD_EVT RXD TXD CLK RTS, CTS SCK MISO, MOSI NPCS[3..0] SCK MISO, MOSI NPCS[3..0] CLK[2..0] A[2..0] B[2..0] SERIAL PERIPHERAL INTERFACE 0 TIMER/COUNTER 0 TWCK TWD TWO-WIRE INTERFACE 2 EXTINT[8:1] NMI External Interrupt Controller POWER MANAGER CLOCK CONTROLLER SLEEP CONTROLLER RESET CONTROLLER GCLK[1..0] RCSYS RC8M XIN[1:0] XOUT[1:0] RC120M OSC0 / OSC1 PLL0 / PLL1 XIN32 XOUT32 32 KHz OSC BODs (1.8V, 3.3V, 5V) SYSTEM CONTROL INTERFACE WATCHDOG TIMER I2S INTERFACE BCLK IWS ISDI ISDO MCLK TWO-WIRE INTERFACE 0/1 TWCK TWD TWALM PULSE WIDTH MODULATION CONTROLLER PWMH[3..0] PWML[3..0] EXT_FAULTS[1:0] supplied by VDDANA DIGITAL TO ANALOG CONVERTER 0/1 DAC0A/B DAC1A/B DACREF ANALOG COMPARATOR 0A/0B/1A/1B AC0AP/N AC0BP/N AC1AP/N AC1BP/N AC0AOUT/AC0BOUT AC1AOUT/AC1BOUT TIMER/COUNTER 1 QUADRATURE DECODER 0/1 ASYNCHRONOUS TIMER FREQUENCY METER A[2..0] B[2..0] CLK[2..0] QEPA QEPB QEPI PA PB PC PD 32117D–AVR-01/12 5 5 Page AT32UC3C 3.2 Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed Signals Each GPIO line can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the GPIO lines. Table 3-1. GPIO Controller Function Multiplexing TQFP G / P Pin QFN 64 TQFP LQFP 100 144 PIN I Type O Supply (1) 1 1 1 PA00 0 VDDIO1 x1/x2 A VDDIO1 2 2 2 PA01 1 x1/x2 VDDIO1 SCIF - 3 3 3 PA02 2 x1/x2 GCLK[0] VDDIO1 SCIF - 4 4 4 PA03 3 x1/x2 GCLK[1] 7 10 21 PA04 4 VDDANA x1/x2 ADCIN0 8 11 22 PA05 5 VDDANA x1/x2 ADCIN1 9 12 23 PA06 6 VDDANA x1/x2 ADCIN2 10 13 24 PA07 7 VDDANA x1/x2 ADCIN3 11 14 25 PA08 8 VDDANA x1/x2 ADCIN4 12 15 26 PA09 9 VDDANA x1/x2 ADCIN5 16 27 PA10 10 VDDANA x1/x2 ADCIN6 17 28 PA11 11 VDDANA x1/x2 ADCIN7 18 29 PA12 12 VDDANA x1/x2 AC1AP0 19 30 PA13 13 VDDANA x1/x2 AC1AN0 20 31 PA14 14 VDDANA x1/x2 AC1BP0 21 32 PA15 15 VDDANA x1/x2 AC1BN0 13 22 33 PA16 16 VDDANA x1/x2 ADCREF0 ADC 14 23 34 REFP ADC 15 24 35 REFN B CANIF - TXLINE[1] CANIF - RXLINE[1] EIC - EXTINT[1] USBC - ID USBC - VBOF AC1AP1 AC1AN1 AC1BP1 AC1BN1 EIC - EXTINT[4] ADCREF1 SPI0 - NPCS[0] SPI0 - NPCS[1] SPI1 - NPCS[0] SPI1 - NPCS[1] GPIO function CD PEVC - PAD_EVT [0] PEVC - PAD_EVT [1] ACIFA0 - ACAOUT ACIFA0 - ACBOUT PEVC - PAD_EVT [2] PEVC - PAD_EVT [3] EIC - EXTINT[2] PEVC - PAD_EVT [13] PEVC - PAD_EVT [14] AC1AP0 or DAC1A ADCIN15 AC1BN0 or DAC1B DACREF E F 32117D–AVR-01/12 11 11 Page

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