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PDF ATA664151 Data sheet ( Hoja de datos )
| Número de pieza | ATA664151 | |
| Descripción | LIN System Basis Chip | |
| Fabricantes | ATMEL Corporation | |
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ATA664151
LIN System Basis Chip with LIN Transceiver, 5V
Regulator, Watchdog, 8-channel High Voltage Switch
Interface with High Voltage Current Sources, 16-bit SPI
DATASHEET
Features
● 8-channel HV switch interface with HV current sources
● Linear low-drop voltage regulator, up to 80mA current capability, VCC = 5.0V ±2%
● Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications
Rev.1.3”
● LIN master and slave operation possible
● Supply voltage up to 40V
● Operating voltage VS = 5V to 27V
● Internal voltage divider for VBattery sensing (±2%)
● 16-bit serial interface (daisy-chain-capable) for configuration and diagnosis
● Typically 8µA supply current during sleep mode
● Typically 35µA supply current in active low-power mode
● VCC-undervoltage detection (4ms reset time) and watchdog reset logical
combined at NRES open drain output
● LIN high-speed mode up to 200kBit/s
● Adjustable watchdog timer via external resistor
● Negative trigger input for watchdog
● LIN physical layer complies with LIN 2.1 specification and SAE J2602-2
● Wake-up capability via LIN bus and CL15
● Bus pin is overtemperature and short-circuit protected versus GND and battery
● Advanced EMC and ESD performance
● Package: QFN32 5x5mm
9268I-AUTO-04/15
1 page  
3. Pin and Functional Description
3.1 Physical Layer Compatibility
Since the LIN physical layer is independent of higher LIN layers (such as the LIN protocol layer), all nodes with a LIN
physical layer as per release version 2.1 can be mixed with LIN physical layer nodes found in older versions (i.e., LIN 1.0,
LIN 1.1, LIN 1.2, LIN 1.3, LIN 2.0), without any restrictions.
3.2 Supply Pin (VS)
The operating voltage is VS = 5V to 27V. An undervoltage detection is implemented to disable data transmission via the
LIN bus and the switch interface if VVS falls below VVSth in order to avoid false bus messages. After switching on VS, the IC
starts in active mode (see also Section 4.1 “Active Mode” on page 9), with the VCC voltage regulator and the window
watchdog switched on (the latter depends on the VDIV pin, see Section 10. “Watchdog” on page 28).
3.3 Ground Pins GND and AGND
The IC is neutral on the LIN pin in the event of GND disconnection. It can handle a ground shift of up to 11.5% of VS.
Note:
Please note that pin AGND is used for internal reference generation. This should be considered when design-
ing the PCB in order to minimize the effect on the voltage thresholds.
3.4 Voltage Regulator Output Pin (VCC)
The internal 5V voltage regulator is capable of driving loads up to 80mA for supplying the microcontroller and other loads on
the PCB. It is protected against overloads by means of current limitation and overtemperature shutdown. In addition, the
output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined threshold
VVCCthun.
A safe operating area (SOA) is defined for the voltage regulator, because the power dissipation caused by this block might
exceed the system’s thermal budget.
3.5 Bus Pin (LIN)
A low-side driver with internal current limitation, thermal shutdown and an internal pull-up resistor in compliance with the
LIN 2.1 specification are implemented. The allowed voltage range is from –30V to +40V. Reverse currents from the LIN bus
to VS are suppressed, even in the event of GND shifts or battery disconnection. The LIN receiver thresholds are compatible
with the LIN protocol specification. The fall time from recessive to dominant bus state and the rise time from dominant to
recessive bus state are slope-controlled.
For higher bit rates the slope control can be switched off by setting the SPI-bit LSME. Then the slope time of the LIN falling
edge is < 2µs. The slope time of the rising edge strongly depends on the capacitive load and the pull-up resistance at the
LIN-line. To achieve a high bit rate it is recommended to use a small external pull-up resistor (500) and a small capacitor.
This allows very fast data transmission up to 200Kbit/s, e.g., for electronic control tests of the ECU, microcontroller
programming or data download. In this High-speed Mode a superior EMC performance is not guaranteed.
Note:
The internal pull-up resistor is only switched on in active mode and when the LIN transceiver is activated by the
LINE-bit (active mode with LIN bus transceiver).
3.6 Bus Logic Level Input Pin (TXD)
The TXD pin is the microcontroller interface for controlling the state of the LIN output. TXD must be pulled to ground in order
to keep the LIN bus in the dominant state. If TXD is high or not connected (internal pull-up resistor), the LIN output transistor
is turned off and the bus is in recessive state.
If configured, an internal timer prevents the bus line from being constantly driven in the dominant state. If TXD is forced to
low for longer than tDOM, the LIN bus driver is switched back to recessive state. TXD has to be switched to high for at least
tTOrel to reactivate the LIN bus driver (by resetting the time-out timer).
As mentioned above, this time-out function can be disabled via the SPI configuration register in order to achieve any long
dominant state on the connected line (such as PWM transmission, or low bit rates).
ATA664151 [DATASHEET]
9268I–AUTO–04/15
5
5 Page 
4.2.2
Wake-up from Sleep Mode via CL15
Voltage above VCL15H at pin CL15 activates a CL15 wake-up detection phase. This state must persist for at least tCLdeb in
order to detect a wake-up. If the pulse is too short, the IC remains in Sleep Mode.
When leaving sleep mode first the VCC voltage regulator is activated to enable the microcontroller supply. Then as soon as
the VCC level reaches valid levels, the VCC startup timer is started. During this time, the NRES pin is kept low in order to
keep the microcontroller from running. This ensures a proper voltage supply and signal stabilization in the application. With
the rising edge at NRES, the SPI is ready for communication and the Atmel® ATA664151 can be initialized.
Figure 4-3. CL15 Wake-up from Sleep Mode
CL15
VCC
NRES
NIRQ
SPI Comm.
Watchdog State
Watchdog off
tCL15deb = 160μs typ
VCC Startup
tnres = 4ms typ
Init IC/ Read Status
Start Watchdog Lead Time
The wake-up behavior is analogous to a wake-up via the LIN bus as seen above. One difference is that no negative edge is
required to start the wake-up procedure as is the case for LIN wake-ups. After the VCC startup time tWDnres has elapsed,
NRES is released and therefore pulled up, either by the internal or additional external resistors. The microcontroller can then
configure the Atmel ATA664151 and thus be notified about the actual status including the wake-up source. Here, the two
status bits “IRQS1” and “IRQS0” read back as '10'.
ATA664151 [DATASHEET]
9268I–AUTO–04/15
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ATA664151.PDF ] | |
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