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PDF LPC812M101JTB16 Data sheet ( Hoja de datos )
| Número de pieza | LPC812M101JTB16 | |
| Descripción | 32-bit ARM Cortex-M0+ microcontroller | |
| Fabricantes | NXP Semiconductors | |
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LPC81xM
32-bit ARM Cortex-M0+ microcontroller; up to 16 kB flash and
4 kB SRAM
Rev. 4.4 — 23 June 2015
Product data sheet
1. General description
The LPC81xM are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at
CPU frequencies of up to 30 MHz. The LPC81xM support up to 16 kB of flash memory
and 4 kB of SRAM.
The peripheral complement of the LPC81xM includes a CRC engine, one I2C-bus
interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up
timer, and state-configurable timer, one comparator, function-configurable I/O ports
through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O
pins.
2. Features and benefits
System:
ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz with
single-cycle multiplier and fast single-cycle I/O port.
ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
System tick timer.
Serial Wire Debug (SWD) and JTAG boundary scan modes supported.
Micro Trace Buffer (MTB) supported.
Memory:
Up to 16 kB on-chip flash programming memory with 64 Byte page write and erase.
Up to 4 kB SRAM.
ROM API support:
Boot loader.
USART drivers.
I2C drivers.
Power profiles.
Flash In-Application Programming (IAP) and In-System Programming (ISP).
Digital peripherals:
High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 18
General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,
programmable open-drain mode, input inverter, and glitch filter.
High-current source output driver (20 mA) on four pins.
High-current sink driver (20 mA) on two true open-drain pins.
GPIO interrupt generation capability with boolean pattern-matching feature on eight
GPIO inputs.
Switch matrix for flexible configuration of each I/O pin function.
1 page  
NXP Semiconductors
6. Block diagram
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
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LPC81XM
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4.4 — 23 June 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
5 of 77
5 Page 
NXP Semiconductors
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
Table 5. Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix)
Function name Type Description
U0_SCLK
I/O Serial clock input/output for USART0 in synchronous mode.
U1_TXD
O Transmitter output for USART1.
U1_RXD
I Receiver input for USART1.
U1_RTS
O Request To Send output for USART1.
U1_CTS
I Clear To Send input for USART1.
U1_SCLK
I/O Serial clock input/output for USART1 in synchronous mode.
U2_TXD
O Transmitter output for USART2.
U2_RXD
I Receiver input for USART2.
U2_RTS
O Request To Send output for USART2.
U2_CTS
I Clear To Send input for USART2.
U2_SCLK
I/O Serial clock input/output for USART2 in synchronous mode.
SPI0_SCK
I/O Serial clock for SPI0.
SPI0_MOSI
I/O Master Out Slave In for SPI0.
SPI0_MISO
I/O Master In Slave Out for SPI0.
SPI0_SSEL
I/O Slave select for SPI0.
SPI1_SCK
I/O Serial clock for SPI1.
SPI1_MOSI
I/O Master Out Slave In for SPI1.
SPI1_MISO
I/O Master In Slave Out for SPI1.
SPI1_SSEL
I/O Slave select for SPI1.
CTIN_0
I SCT input 0.
CTIN_1
I SCT input 1.
CTIN_2
I SCT input 2.
CTIN_3
I SCT input 3.
CTOUT_0
O SCT output 0.
CTOUT_1
O SCT output 1.
CTOUT_2
O SCT output 2.
CTOUT_3
O SCT output 3.
I2C0_SCL
I/O I2C-bus clock input/output (open-drain if assigned to pin PIO0_10).
High-current sink only if assigned to PIO0_10 and if I2C Fast-mode
Plus is selected in the I/O configuration register.
I2C0_SDA
I/O I2C-bus data input/output (open-drain if assigned to pin PIO0_11).
High-current sink only if assigned to pin PIO0_11 and if I2C
Fast-mode Plus is selected in the I/O configuration register.
ACMP_O
O Analog comparator digital output.
CLKOUT
O Clock output.
GPIO_INT_BMAT O
Output of the pattern match engine.
LPC81XM
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4.4 — 23 June 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
11 of 77
11 Page | ||
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