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PDF MH2511SC Data sheet ( Hoja de datos )

Número de pieza MH2511SC
Descripción Easy Multi Interleave Controller
Fabricantes Shindengen 
Logotipo Shindengen Logotipo



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MH2501SC/MH2511SC APPLICATION NOTE
Easy Multi Interleave
Controller for multi-phase
interleaved PFC
JUL.2012 Ver.1.0
®
Application Note ver.1.0
Shindengen Electric Manufacturing Co., Ltd.
SHINDENGEN
ELECTRIC MFG.CO.,LTD
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1 page




MH2511SC pdf
1 Outline
MH2501SC (“master IC” hereinafter) and MH2511SC (“slave IC” hereinafter) comprise ICs for a
current-critical interleaved PFC circuit. Interleaving with master and slave ICs ensures low noise
and high efficiency, which are characteristics of current-critical PFCs, even in high power regions.
One-phase PFC can be configured using just the master IC.
1.1 Features
1. High efficiency and low noise via master-slave interleaved critical current mode
2. Two or greater phase interleaving achieved by connecting slave ICs in parallel
3. One-phase PFC configurable using just the master IC
4. Support for wide range of input voltages with guaranteed VCC withstand voltage of 26 V
5. Variety of protective functions
(overvoltage protection, overcurrent protection, feedback open/short protection, and output
diode short protection)
1.2 Block diagram
Fig. 1 Master IC (MH2501SC) block diagram
IL_IN 1
LATCH 3
TIMER 5
GND 6
IL_IN
EDGE OUT
Phase
Shifter
Master_ON
Timer_F/F
SQ
RQ
Master_ON
Counter_F/F
SQ
RQ
Master_ON
Timer 50us
Slave_Stop1_F/F
QS
QR
-
+ TIMER
Slave_Stop2_F/F
QS
QR
ON/OFF_F/F
SQ
RQ
Vcc
DRIVER
Vcc_UVLO
+
OCL -
Fig. 2 Slave IC (MH2511SC) block diagram
2 IL_OUT
7 OUT
8 VCC
4 OCL
SHINDENGEN
ELECTRIC MFG.CO.,LTD
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MH2511SC arduino
2.4 Startup and shutdown sequences Master Slave
Fig. 10 shows the startup and shutdown sequences for interleaved operation. VCC is common to
the master IC and slave IC.
ACin
0V
Vo
Vo_ref×1.08V
Vo_ref
FB 0.4V
VCC
VCC(start)M
VCC(start)S
COMP
1.2V
OUT(M)
OVP operation
0V
VCC(stop)M
VCC(stop)S
0V
0V
0V
0V
OUT(S)
Fig. 10 Startup and shutdown sequences
0V
(a) Oscillation start sequence
(1) When a voltage is applied to the VCC pin, the COMP is charged to 1.2 V.
(2) When the VCC voltage reaches VCC(start)S, the slave IC starts up. However, the
gate signal is not output, since the master IC has not started up.
(3) When the VCC voltage reaches VCC(start)M, the master IC also starts up and
starts the gate output. The slave IC also starts gate output.
(4) Immediately after startup, gate output stops due to the OVP operation, suppressing
an increase in output voltage.
(b) Oscillation stop sequence
(1) When the VCC voltage has fallen to VCC(stop)M, the master IC shuts down and
stops the gate output. The slave IC also stops the gate output. The COMP voltage
is clamped to 1.2 V.
(2) When the VCC voltage has fallen to VCC(stop)S, the slave IC shuts down.
SHINDENGEN
ELECTRIC MFG.CO.,LTD
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