PDF TW2968 Data sheet ( Hoja de datos )

Número de pieza	TW2968
Descripción	8-Channel WD1 (960H)/D1 Compatible Video Decoders and Audio Codecs
Fabricantes	Intersil
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No Preview Available ! 8-Channel WD1 (960H)/D1 Compatible Video Decoders and Audio Codecs TW2968 Features Video Decoder  WD1 (960H) and D1 compatible video decoding operation and each channel is programmable  NTSC (M, 4.43) and PAL (B, D, G, H, I, M, N, N combination), PAL (60) support with automatic format detection  Built-in analog anti-alias filter  Eight 10-bit ADCs and analog clamping circuit for CVBS input  Fully programmable static gain or automatic gain control for the Y channel  Programmable white peak control for CVBS channel  4-H adaptive comb filter Y/C separation  PAL delay line for color phase error correction  Image enhancement with peaking and CTI  Digital sub-carrier PLL for accurate color decoding  Digital Horizontal PLL for synchronization processing and pixel sampling  Advanced synchronization processing and sync detection for handling non-standard and weak signal  Programmable hue, brightness, saturation, contrast, sharpness  Automatic color control and color killer  ITU-R 656 like YCbCr (4:2:2) output or time multiplexed output with 36/72/144MHz for WD1 or 27/54/108MHz for D1 format Audio Codec  Ten integrated audio ADCs processing and one audio DAC  Provides multi-channel audio mixed analog output  Supports I2S/DSP Master/Slave interface for record output and playback input  PCM 8/16-bit and u-Law/A-Law 8-bit for audio word length  Programmable audio sample rate that covers popular frequencies of 8/16/32/44.1/48kHz Miscellaneous  Embedded PTZ Tx pulse generation  Two-wire MPU serial bus interface  Integrated clock PLL for 144/108MHz clock output  Power save and Power down mode  Low power consumption  Single 27MHz crystal for all standards and both WD1 and D1 format  3.3V tolerant I/O  1.0V/3.3V power supply  128-pin LQFP package (pin compatible with TW2964 128-LQFP version) FN8394.4 1 April 15, 2014 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 \| Copyright Intersil Americas LLC 2014. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. 1 page TW2968 0x72 – Mix Ratio Value 1 ...................................................84 0x72 – Mix Ratio Value 2 ...................................................85 0x73 – A51DET_ENA .......................................................86 0x74 – Status of Audio 51 Detection ................................86 0x7B – ADATM I2S Output Select ....................................87 0x7C – ADATM I2S Output Select ....................................87 0x7D – AIN51/52/53/54 Record Output ............................88 0x7E – A5OUTOFF............................................................89 0x80 – Software Reset Control Register ...........................90 0x81 – Analog Control Register.........................................91 0x82 – Analog Control ReGister2......................................91 0x83 – Control Register I ...................................................92 0x84 – Color Killer Hysteresis Control Register ................92 0x85 – Vertical Sharpness .................................................93 0x86 – Coring Control Register..........................................93 0x87 – Clamping Gain........................................................93 0x88 – Individual AGC Gain...............................................93 0x89 – Audio Fs Mode Control ..........................................94 0x8A – White Peak Threshold ...........................................94 0x8B– Clamp level .............................................................95 0x8C– Sync Amplitude.......................................................95 0x8D – Sync Miss Count Register.....................................95 0x8E – WD1 Clamp Position Register...............................95 0x8F – Vertical Control I.....................................................96 0x90 – Vertical Control II....................................................96 0x91 – Color Killer Level Control .......................................96 0x92 – Comb Filter Control ................................................97 0x93 – VSAVE1..................................................................97 0x94 – Miscellaneous Control I..........................................97 0x95 – LOOP Control Register..........................................98 0x96 – Miscellaneous Control II.........................................99 0x97 – CLAMP MODE.................................................... 100 0x98 – HSLOWCTL ........................................................ 100 0x99 – HSBEGIN ............................................................ 100 0x9A – HSEND................................................................ 100 0x9B – OVSDLY ............................................................. 101 0x9C – OVSEND............................................................. 101 0x9E – NOVID................................................................. 102 0x9F – Clock Output Delay Control Register ................. 103 0xA8 – HFLT12 ............................................................... 103 0xA9 – HFLT34 ............................................................... 103 0xAF – Vertical Peaking Level Control 12...................... 104 0xB0 – Vertical Peaking Level Control 34 ...................... 104 0xB1 – TESTVNUM........................................................ 105 0xB2 – VDLOSS Output ................................................. 106 0xB3 – Audio ADC Digital Input Offset Control ............. 106 0xB4 – Audio ADC Digital Input Offset Control .............. 106 0xB5 – Audio ADC Digital Input Offset Control .............. 107 0xB6 – Audio ADC Digital Input Offset Control .............. 107 0xB7 – Audio ADC Digital Input Offset Control .............. 107 0x75 – Audio ADC Digital Input Offset Control ............. 107 0x76 – Audio ADC Digital Input Offset Control .............. 107 0xB8 – Analog Audio ADC Digital Output Value............ 108 0xB9 – Analog Audio ADC Digital Output Value............ 108 0xBA – Analog Audio ADC Digital Output Value ........... 108 0xBB – Analog Audio ADC Digital Output Value ........... 108 0xBC – Analog Audio ADC Digital Output Value ........... 108 0x77 – Analog Audio ADC Digital Output Value ........... 109 0x78 – Analog Audio ADC Digital Output Value ............ 109 0xBD – Adjusted Analog Audio ADC Digital Input Value109 0xBE – Adjusted Analog Audio ADC Digital Input Value109 0xBF – Adjusted Analog Audio ADC Digital Input Value110 0xC0 – Adjusted Analog Audio ADC Digital Input Value110 0xC1 – Adjusted Analog Audio ADC Digital Input Value110 0x79 – Adjusted Analog Audio ADC Digital Input Value110 0x7A – Adjusted Analog Audio ADC Digital Input Value 110 0xC8 – MPP Output Mode Control................................. 111 0xC9 – MPP Pin Output Mode Control .......................... 112 0xCB –POLMPP ............................................................. 113 0xCC – H960EN.............................................................. 114 0xCD – O36M ..................................................................115 0xCE – Analog Power Down Control..............................116 0xCF – Serial Mode Control ............................................117 0xD0, 0xD1, 0x7F - Analog Audio Input Gain.................118 0xD2 – Number of Audio to be Recorded.......................119 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA – Sequence of Audio to be Recorded................................120 0xDB –Master Control .....................................................121 0xDC –u-Law/A-Law Output and Mix Mute Control .......122 0xDD – Mix Ratio Value ..................................................122 0xDE – Mix Ratio Value...................................................122 0xDF – Analog Audio Output Gain.................................123 0xE0 – Mix Output Selection 1.......................................123 0xE0 – Mix Output Selection 2.......................................124 0xE1 – Audio Detection Period and Audio Detection Threshold .........................................................................125 0xE2 – Audio Detection Threshold.................................126 0xE3 – Audio Detection Threshold.................................126 0xE4 – YDLY12 ..............................................................126 0xE5 – YDLY34 ..............................................................126 0xE7 – Video output mode.............................................127 0xE8 – VD1 output CH12 select ....................................128 0xE9 – VD1 output CH34 select ....................................128 0xEA – VD2 output CH12 select....................................129 0xEB – VD2 output CH34 select....................................129 0xEC – VD3 output CH12 select....................................130 0xED – VD3 output CH34 select....................................130 0xEE – VD4 output CH12 select....................................131 0xEF – VD4 output CH34 select ....................................131 0xF0 – Audio Clock Increment .......................................132 0xF1 – Audio Clock Increment .......................................132 0xF2 – Audio Clock Increment .......................................132 0xF3 – Audio Clock Number ..........................................133 0xF4 – Audio Clock Number ..........................................133 0xF5 – Audio Clock Number ..........................................133 0xF6 – Serial Clock Divider ............................................133 0xF7 – Left/Right Clock Divider......................................133 0xF8 – Audio Clock Control............................................134 0xF9 – Video Miscellaneous Function Control ..............135 0xFA – Output Enable Control and Clock Output Control136 0xFB – Clock Polarity Control.........................................137 0xFC – Enable Video and Audio Detection ...................138 0xFD – Status of Video and Audio Detection ................138 0xFE – Device ID and Revision ID Flag.........................139 0xFF – Device ID and Revision ID Flag.........................139 Page1 Registers..................................................................139 0x00(VIN5)/0x10(VIN6)/0x20(VIN7)/0x30(VIN8) – Video Status Register.................................................................140 0x01(VIN5)/0x11(VIN6)/0x21(VIN7)/0x31(VIN8) – BRIGHTNESS Control Register......................................140 0x02(VIN5)/0x12(VIN6)/0x22(VIN7)/0x32(VIN8) – CONTRAST Control Register .........................................140 0x03(VIN5)/0x13(VIN6)/0x23(VIN7)/0x33(VIN8) – SHARPNESS Control Register.......................................141 0x04(VIN5)/0x14(VIN6)/0x24(VIN7)/0x34(VIN8) – Chroma (U) Gain Register .............................................................141 0x05(VIN5)/0x15(VIN6)/0x25(VIN7)/0x35(VIN8) – Chroma (V) Gain Register .............................................................141 0x06(VIN5)/0x16(VIN6)/0x26(VIN7)/0x36(VIN8) – Hue Control Register ...............................................................142 0x07(VIN5)/0x17(VIN6)/0x27(VIN7)/0x37(VIN8) – Cropping Register, High ..................................................142 0x08(VIN5)/0x18(VIN6)/0x28(VIN7)/0x38(VIN8) – Vertical Delay Register, Low.........................................................142 0x09(VIN5)/0x19(VIN6)/0x29(VIN7)/0x39(VIN8) – Vertical Active Register, Low ........................................................142 0x0A(VIN5)/0x1A(VIN6)/0x2A(VIN7)/0x3A(VIN8) – Horizontal Delay Register, Low.......................................143 0x0B(VIN5)/0x1B(VIN6)/0x2B(VIN7)/0x3B(VIN8) – Horizontal Active Register, Low ......................................143 5 5 Page TW2968 Video Output Format The TW2968 supports ITU-R BT.656 like format. All video data and timing signal of four channels are synchronous with the pins CLKPO or CLKNO output. Therefore, CLKPO or CLKNO can be connected to four channel interfaces for synchronizing data. TOTAL PIXEL PER HORIZONTAL LINE The number of total pixel per horizontal line depends on Horizontal line frequency of video input signal incoming in VINn pin. As standard, if 27MHz/54MHz/108MHz output mode(O36Mn=0),60Hz video has 858x2 27MHz clocks,50Hz video has 864x2 27MHz clocks.If 36MHz/72MHz/144MHz output mode(O36Mn=1),60Hz video has 1144x2 36MHz clocks,50Hz video has 1152x2 36MHz clocks. CHANNEL ID The channel ID can be inserted in the data stream using the CHID_MD register. Two kinds of channel ID format can be supported. One is horizontal blanking code with channel ID and the other is ITU-R BT.656 sync code with channel ID. Each ITU-R BT.656 like data stream in 4x output data, 2x output data can have this Sync Code and Blanking Code. Table 2 shows this Channel ID format. Nibble data value m shows Video Decoder number to be output in this video stream. TABLE 2. THE CHANNEL ID FORMAT FOR 4X960H, 2X960H TIME-MULTIPLEXED FORMAT CONDITION 656 FVH VALUE SAV/EAV CODE SEQUENCE Field Vtime Htime F V H First Second Third Fourth EVEN Blank EAV 1 1 EVEN Blank SAV 1 1 EVEN Active EAV 1 0 EVEN Active SAV 1 0 ODD Blank EAV 0 1 ODD Blank SAV 0 1 ODD Active EAV 0 0 ODD Active SAV 0 0 (a) ITU-R BT.656 Sync Code with Channel ID VIDEO Y VINn 8’h1m (b) Horizontal Blanking Code with Channel ID 1 0xFF 0x00 0x00 0 0xFF 0x00 0x00 1 0xFF 0x00 0x00 0 0xFF 0x00 0x00 1 0xFF 0x00 0x00 0 0xFF 0x00 0x00 1 0xFF 0x00 0x00 0 0xFF 0x00 0x00 0xFm 0xEm 0xDm 0xCm 0xBm 0xAm 0x9m 0x8m H BLANKING CODE WITH CHANNEL ID CB CR 8’h8m 8’h8m As default, m = 0 VIN1 656 data, m = 1 VIN2 656 data, m = 2 VIN3 656 data, m = 3 VIN4 656 data,m=4 VIN5 656 data,m=5 VIN6 656 data,m=6 VIN7 656 data,m=7 VIN8 656 data.CH1NUM, CH2NUM, CH3NUM, CH4NUM ,CH5NUM,CH6NUM,CH7NUM and CH8NUM registers can change this m value in each video channel output data if necessary. 11 11 Page

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