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PDF EN71NS032A0 Data sheet ( Hoja de datos )
| Número de pieza | EN71NS032A0 | |
| Descripción | Stacked Multi-Chip Product (MCP) Flash Memory and RAM | |
| Fabricantes | Eon Silicon Solution | |
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EN71NS032A0
EN71NS032A0
Stacked Multi-Chip Product (MCP) Flash Memory and RAM
32 Megabit (2M x 16-bit) CMOS 1.8 Volt-only Burst Simultaneous
Operation, Multiplexed Flash Memory and
16 Megabit (1M x 16-bit) Pseudo Static RAM
Distinctive Characteristics
MCP Features
■ Power supply voltage of 1.7V to 1.95V
■ High performance
- 70 ns @ random access
- 7 ns @ burst access (108MHz)
■ Package
- 6.2 x 7.7 x 1.0mm 56 ball BGA
■ Operating Temperature
- 25°C to +85°C
General Description
EN71NS032A0 is a product line of stacked Multi-Chip Product (MCP) packages and consists of:
■ Burst Simultaneous Operation, Multiplexed NOR Flash Memory.
■ Burst Mode, Multiplexed Pseudo SRAM.
For detailed specifications, Please refer to the individual datasheets listed in the following table.
Device
NOR Flash Memory
Pseudo SRAM
Document
EN29NS032
ENPSS16
Flash Density
Flash Access time
Flash Burst mode
max frequency
Package
32Mb
70ns at Async. Mode
7ns at Burst Read
108MHz
56-ball BGA
pSRAM density
pSRAM Access time
pSRAM Burst mode
max frequency
16Mb
70ns at Async. Mode
7ns at Burst Read
108MHz
This Data Sheet may be revised by subsequent versions
1
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2011/07/05
1 page  
Operating Mode (For Asynchronous mode)
EN71NS032A0
Asynchronous Mode
BCR[15]=1
Read
Power
Active
CLK ADV#
CE#
OE#
WE#
CRE
UB#/
LB#
WAIT2
A/DQ[15:0
]
Note
X L L H L L Low-z Data out 4
Write
Active
X
L X L L L High-z Data in
4
Standby
Standby H or L X H X X L X High-z High-z 5, 6
No operation
Idle
X X L X X L X Low-z
X
4, 6
Configuration register
write
Configuration register
read
DPD
Active
Active
Deep
Power-down
X
X
L
L H L H X Low-z High-z
L
L HH
L
Low-z
Config.
Reg.out
X H X X X X High-z High-z
7
Operating Mode (For Synchronous Burst mode)
Burst Mode
BCR[15]=0
Async read
Async write
Power
Active
Active
CLK ADV#
CE#
OE#
WE#
CRE
UB#/
LB#
WAIT A/DQ[15:0] Note
H or L
L L H L L Low-z Data out 4, 8
H or L
L X L L L High-z Data in
4
Standby
Standby H or L X H X X L X High-z High-z 5, 6
No operation
Idle H or L X L X X L X Low-z
X
4, 6
Initial burst read
Active
L L X H L L Low-z Address 4, 9
Initial burst write
Active
L L H L L X Low-z Address 4, 9
Burst continue
Active
Data out
H L X X X L Low-z
or
4, 9
Data in
Configuration register
write
Active
L L H L H X Low-z High-z 9. 10
Configuration register
read
Active
L
L
L HH
L
Low-z
Config.
Reg.out
9, 10
DPD
Deep
Power-down
L
X
H X X X X High-z High-z
7
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5 ©2004 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2011/07/05
www.eonssi.com
5 Page | ||
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| PDF Descargar | [ Datasheet EN71NS032A0.PDF ] | |
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