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PDF IP1718LF Data sheet ( Hoja de datos )
| Número de pieza | IP1718LF | |
| Descripción | 18-port 10/100Mbps Smart Switch Controller | |
| Fabricantes | IC Plus | |
| Logotipo |  |
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IP1718 LF
Preliminary Data Sheet
18-port 10/100Mbps Smart Switch Controller
Features
Embeds 1.5 Mb packet buffer
Handles up to 4K MAC address entries
Supports non-blocking wire speed operation
Provides 16-port SS-SMII and 2-port MII
Supports 2 ports selectable normal MII,
reverse MII
All I/O signals can operate at 3.3V or 1.8V.
Supports up to 18 port based VLAN group
Supports 256 levels of data rate control
Captures BPDU, IGMP and OSPF …packet
and forward to the CPU port.
Suppress/enable per port address learning.
Embeds two levels of priority queues for VLAN
tag, physical port and IP Differentiated Service.
Supports flexible port trunking configuration: up
to 3 groups and up to 4 ports for each group
Embeds an internal regulator controller to
simplify the system design.
Power supply: 1.8V for core logic; optional
3.3V or 1.8V for I/O.
128 pin QFP package
Adjustable I/O driving capability
Support packet length up to 1536 Bytes
Spanning Tree state support.
Supports 3 kinds of port mirrioring methods
HOL blocking prevention
Only one 25MHz crystal needed
Broadcast storm control support
Programmable MAC address table through 2
serial pins.
Support Lead Free package (Please refer to
the Order Information)
General Description
Supporting 16-port SS-SMII, 2-port MII and
various advanced features, the IP1718 LF fits both
the office switch and the ETTH( Ethernet to the
Home) application. The IP1718 LF embeds
internal SSRAM for the use of the packet buffer
and the MAC address table. Besides the
traditional switch functions, the IP1718 LF
provides the easy-to-design solution, fitting the
requirement of most switch application.
The IP1718 LF also supports some features which
can simplify the customer’s design from the
viewpoint of the system. The embedded regulator
controller can reduce the component number on
the system board. The web management can be
easily accomplished by adding an external CPU
with protocol stack. All the I/O pins can operate at
3.3V or 1.8V, providing more design flexibility for
power supply distribution.
The IP1718 LF embeds 1.5Mb internal packet
buffer and stores up to 4K MAC address entries,
making it suitable for the generic switch
application. In addition, the IP1718 LF supports a
wide range of data rate for both egress and
ingress, which is useful in the ETTH(Ethernet to
the Home) application. The higher layer data
packet such as BPDU, IGMP, OSPF can be
forwarded to either the 17th or 18th (CPU) port. The
flexible trunk configuration allows the user to scale
the switch interconnection bandwidth. When the
port mirroring function is enabled, the data traffic
on the source port will be forwarded to a specified
destination port, making the switch administration
easier. Supporting up to 18 port based VLAN
groups, the IP1718 LF can be configured to fit
various traffic partitions. The CoS function is
accomplished by configuring the priority of the
physical port, the 802.1Q VLAN tag and IP
DSCP(Differentiated Service Code Point). In order
to fit the application of some special environment,
the address learning and the MAC address table
aging can be disabled.
Copyright © 2003, IC Plus Corp.
1/33
January 27, 2005
IP1718 LF-DS-R05
1 page  
2 Block Diagram
PLL/ Clock
generator
Regulator
EEPROM
CPU Interface
PHY
Control
I/F
Register
IP1718 LF
Preliminary Data Sheet
Frame Buffer
Memory controller/ BIST
Tx/Rx FIFO/DMA
MAC Address
Table
Address
Resolution
Engine
10/100M ... 10/100M
MAC
MAC
Copyright © 2003, IC Plus Corp.
5/33
January 27, 2005
IP1718 LF-DS-R05
5 Page 
IP1718 LF
Preliminary Data Sheet
4 Functional Description
4.1 Medium Access Control(MAC)
4.1.1 Data Rate Control
The IP1718 LF implements a sophisticated data rate control mechanism, which is very useful for the
bandwidth-limited network. By controlling both the ingress data rate and the egress data rate, the IP1718
LF provides a variety of the bandwidth configuration.
By means of calculating the maximum TX/RX byte number in a time unit of the corresponding port, the
IP1718 LF provides a precise bandwidth control mechanism. The formula for calculating the maximum
byte during a time unit is:
M.B.N= S.D.R* 512
Where M.B.N stands for the maximum byte number; S.D.R the specified data rate.
The time unit is 10ms at 100 Mbps speed and 100ms at 10Mbps speed.
The data rate for each port is specified in registers ranging from 03H to 12H and 1BH ~ 1CH.
If the transmit/receive byte number reaches the specified M.B.N after the transmit/receive timer expires,
the MAC will continue the operation until the whole data packet is transmitted/received and then wait until
the next time unit starts.
For example, if the value set to register 06H is 12H(18 in decimal) and the port 1 runs at 100Mbps speed,
the maximum byte number allowed to transmit through port 1 is 9216 bytes(the result of 512*18) within
10ms( 1,000,000 bit time). 9216 bytes stands for 73,728 bit time. The flow control mechanism will be
activated for the spare time. Thus the data rate can be limited to a specified value.
4.1.2 Flow Control
The IP1718 LF embeds the flow control mechanism for both full duplex mode and half duplex mode. When
the buffer reach a pre-defined level, the transmit MAC will generate the flow control pattern to prevent the
buffer overflow. These flow control patterns are dependent on the duplex mode. The IP1718 LF transmit
MAC generates the backpressure pattern in half duplex mode and the 802.3x pause packet in full duplex
mode.
When operating in half duplex mode, the IP1718 LF should comply with CSMA/CD standard. The
transmit MAC will generate the jam pattern to inform the link partner that the receive buffer is not
available when the buffer reaches a pre-defined level. The IP1718 LF supports the collision_based
backpressure. When the collision_based backpressure is enabled, the transmit MAC of the IP1718 LF
will generate the jam pattern only when the link partner is transmitting data and the buffer is not available.
When detecting the collision on line, the link partner will back off the transmission and then wait until the
back off time expires.
The IP1718 LF uses 802.3x pause packet to accomplish the flow control for full duplex mode. When the
buffer reach a pre-defined level, the transmit MAC generates a Xoff pause packet immediately or right
after the current packet has been transmitted. When receiving a pause packet, the link partner will stop
the transmission for a time period according to the pause value carried by the pause packet, preventing
the internal buffer from overrun.
Copyright © 2003, IC Plus Corp.
11/33
January 27, 2005
IP1718 LF-DS-R05
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IP1718LF.PDF ] | |
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