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PDF CE5039 Data sheet ( Hoja de datos )
| Número de pieza | CE5039 | |
| Descripción | DVB-S Digital Satellite Tuner | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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CE5039
DVB-S Digital Satellite Tuner
with RF Bypass
Data Sheet
Features
• Direct conversion tuner for quadrature down
conversion from L-band to Zero IF
• Symbol rate 1-45 MSps
• Excellent sensitivity <-84.5 dBm at 27.5 MSps
• Independent RF AGC and baseband gain control
• Fifth order baseband filters with bandwidth
adjustable from 6 to 43 MHz
• Fully integrated alignment-free low phase noise
local oscillator
• Selectable RF Bypass
• I2C compatible control
• 3.3 Volt Supply
• 28 pin 5x5 mm QFN Package
Applications
• DVB-S Free-to-Air Satellite receiver systems
• 8PSK Satellite Receiver Systems
February 2006
Ordering Information
HGCE5039 882365
28 Pin QFN Trays
HGCE5039 S L9F6 882327 28 Pin QFN Tape & Reel
WGCE5039 882560
28 Pin QFN* Trays
WGCE5039 S L9FW 882559 28 Pin QFN* Tape & Reel
*Pb Free Matte Tin
-10°C to +85°C
Description
The CE5039 is a fully integrated direct conversion
tuner for digital satellite receiver systems, targeted
primarily at free-to-air DVB-S receivers where high
sensitivity is a priority. The device also contains a RF
Bypass for connecting to a second receiver module.
The CE5039 is simple to use, requiring no alignment or
tuning algorithms and uses a minimum number of
external components. The device is programmable via
a I2C compatible bus.
A complete reference design (CE9541) is available
using CE6313 demodulator.
RF Input
CE5039
Bypass
Output
Quadrature
VCO
PLL
RF AGC
I
Q
I2C
Control
Loop
Filter
Crystal
Figure 1 - Basic Block Diagram
1
Intel Corporation
D55747-001
Intel and the Intel logo are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others. Copyright © 2006 Intel Corporation. All rights reserved.
1 page  
CE5039
Data Sheet
VccRF1
VccRF2
RFAGC
RFIN
LNA
AGC
RFBYPASS
VccLO
LOTEST
Vvar
PAD/REF
VccVCO
VccDIG
SDA
SCL
SLEEP
XTAL
XCAP
(PADDLE)
VCO
BANK
REF
OSC
BF
BANDWIDTH
ADJUST
FILTER
DC
CORRECTION
DC
CORRECTION
FILTER
90 deg
0 deg
PHASE
SPLITTER
LOCK
DETECT
15 BIT
PROGRAMMABLE
DIVIDER
I2C BUS
INTERFACE
Fpd
CHARGE
PUMP
Fcomp
PORT
INTERFACE
VccBB
QOUT
QOUT
IOUT
IOUT
VccCP
PUMP
P0
REFERENCE DIVIDER
Figure 3 - Detailed Block Diagram
5
Intel Corporation
5 Page 
CE5039
Data Sheet
The R[3:0] bits select the Reference Divider divide ratio. The ratio selected is not a simple binary power-of-two
value but through a lookup table, see Table 7- PLL Reference Divider Ratios.
Division
R3 R2 R1 R0
Ratio
00002
00014
00108
0 0 1 1 16
0 1 0 0 32
0 1 0 1 64
0 1 1 0 128
0 1 1 1 256
10003
10015
1 0 1 0 10
1 0 1 1 20
1 1 0 0 40
1 1 0 1 80
1 1 1 0 160
1 1 1 1 320
Table 7 - PLL Reference Divider Ratios
Bit Field
Name
Default
Type
Description
7:0
-
0X40
R/W Test Modes
Table 8 - Register 3
This register controls test modes within the PLL. This should be programmed with the default settings.
2.2 RF Control Register
A single register controls RF programmability.
Bit Field
7
6:2
1
0
Name
-
-
LEN
-
Default
Type
Description
- R Test Modes
11011
R/W Test Modes
1 R/W Bypass Enable
0 R/W Not used
Table 9 - Register 4
11
Intel Corporation
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CE5039.PDF ] | |
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