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PDF ATmega165PA Data sheet ( Hoja de datos )
| Número de pieza | ATmega165PA | |
| Descripción | 8-bit Atmel Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Atmel ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
8-bit Atmel Microcontroller with 16/32/64KB In-System Programmable Flash
DATASHEET
Features
• High performance, low power Atmel® AVR® 8-Bit Microcontroller
• Advanced RISC architecture
– 130 powerful instructions – most single clock cycle execution
– 32 × 8 general purpose working registers
– Fully static operation
– Up to 16MIPS throughput at 16MHz (Atmel ATmega165PA/645P)
– Up to 20MIPS throughput at 20MHz (Atmel
ATmega165A/325A/325PA/645A/3250A/3250PA/6450A/6450P)
– On-chip 2-cycle multiplier
• High endurance non-volatile memory segments
– In-system self-programmable flash program memory
• 16KBytes (ATmega165A/ATmega165PA)
• 32KBytes (ATmega325A/ATmega325PA/ATmega3250A/ATmega3250PA)
• 64KBytes (ATmega645A/ATmega645P/ATmega6450A/ATmega6450P)
– EEPROM
• 512Bytes (ATmega165A/ATmega165PA)
• 1Kbytes (ATmega325A/ATmega325PA/ATmega3250A/ATmega3250PA)
• 2Kbytes (ATmega645A/ATmega645P/ATmega6450A/ATmega6450P)
– Internal SRAM
• 1KBytes (ATmega165A/ATmega165PA)
• 2KBytes (ATmega325A/ATmega325PA/ATmega3250A/ATmega3250PA)
• 4KBytes (ATmega645A/ATmega645P/ATmega6450A/ATmega6450P)
– Write/erase cycles: 10,000 flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C (1)
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True read-while-write operation
– Programming lock for software security
• Atmel QTouch® library support
– Capacitive touch buttons, sliders and wheels
– Atmel QTouch and QMatrix acquisition
– Up to 64 sense channels
• JTAG (IEEE std. 1149.1 compliant) interface
– Boundary-scan capabilities according to the JTAG standard
– Extensive on-chip debug support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real time counter with separate oscillator
– Four PWM channels
– 8-channel, 10-bit ADC
8285F–AVR–08/2014
1 page  
2. Overview
The Atmel ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P is a low-power CMOS 8-bit
microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle,
this microcontroller achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power
consumption versus processing speed.
2.1 Block diagram
Figure 2-1. Block diagram.
GND
VCC
AVCC
AGND
AREF
PF0 - PF7
PA0 - PA7
PC0 - PC7
PORTF DRIVERS
DATA REGISTER
PORTF
DATA DIR.
REG. PORTF
PORTA DRIVERS
PORTC DRIVERS
DATA REGISTER
PORTA
DATA DIR.
REG. PORTA
DATA REGISTER
PORTC
8-BIT DATA BUS
DATA DIR.
REG. PORTC
ADC
JTAG TAP
PROGRAM
COUNTER
STACK
POINTER
ON-CHIP DEBUG
BOUNDARY-
SCAN
PROGRAMMING
LOGIC
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
AVR CPU
STATUS
REGISTER
USART
UNIVERSAL
SERIAL INTERFACE
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
MCU CONTROL
REGISTER
TIMER/
COUNTERS
INTERRUPT
UNIT
EEPROM
CALIB. OSC
OSCILLATOR
TIMING AND
CONTROL
SPI
DATA REGISTER
PORTE
DATA DIR.
REG. PORTE
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
DATA REG. DATA DIR.
PORTG REG. PORTG
PORTE DRIVERS
PORTB DRIVERS
PORTD DRIVERS
PORTG DRIVERS
PE0 - PE7
PB0 - PB7
PD0 - PD7
PG0 - PG4
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one
single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
Atmel-8285F–AVR-ATmega–08/2014
5
5 Page 
7. AVR CPU core
7.1 Introduction
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure
correct program execution. The CPU must therefore be able to access memories, perform calculations, control
peripherals, and handle interrupts.
7.2 Architectural overview
Figure 7-1. Block diagram of the AVR architecture.
Data Bus 8-bit
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Status
and Control
32 x 8
General
Purpose
Registrers
ALU
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
Data
SRAM
EEPROM
I/O Module1
I/O Module 2
I/O Module n
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories
and buses for program and data. Instructions in the program memory are executed with a single level pipelining.
While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable
Flash memory.
The fast-access Register File contains 32 × 8-bit general purpose working registers with a single clock cycle
access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
Atmel-8285F–AVR-ATmega–08/2014
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ATmega165PA.PDF ] | |
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