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PSD813F1V fiches techniques PDF

STMicroelectronics - Flash in-system programmable peripherals

Numéro de référence PSD813F1V
Description Flash in-system programmable peripherals
Fabricant STMicroelectronics 
Logo STMicroelectronics 





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PSD813F1V fiche technique
PSD813F1V
Flash in-system programmable (ISP) peripherals
for 8-bit MCUs, 3.3 V
NOT FOR NEW DESIGN
FEATURES SUMMARY
DUAL BANK FLASH MEMORIES
Figure 1. Packages
– 1 Mbit of Primary Flash Memory (8
Uniform Sectors)
)– 256 Kbit Secondary EEPROM (4 Uniform
t(sSectors)
– Concurrent operation: read from one
ucmemory while erasing and writing the
dother
ro )16 Kbit SRAM
P t(sPLD WITH MACROCELLS
te c– Over 3,000 Gates Of PLD: DPLD and
le uCPLD
d– DPLD - User-defined Internal chip-select
so rodecoding
b P– CPLD with 16 Output Macrocells (OMCs)
- O teand 24 Input Macrocells (IMCs)
27 RECONFIGURABLE I/Os
) le– 27 individually configurable I/O port pins
t(s sothat can be used for the following
c bfunctions:
u OMCU I/Os;
d -PLD I/Os;
ro )Latched MCU address output; and
P t(sSpecial function I/Os.
te cNote: 16 of the I/O ports may be
le uconfigured as open-drain outputs.
so rodENHANCED JTAG SERIAL PORT
– Built-in JTAG-compliant serial port allows
b Pfull-chip In-System Programmability (ISP)
O te– Efficient manufacturing allows for easy
leproduct testing and programming
oPAGE REGISTER
s– Internal page register that can be used to
b expand the microcontroller address space
O by a factor of 256.
PQFP52 (M)
PLCC52 (J)
TQFQ64 (U)
HIGH ENDURANCE:
– 100,000 Erase/WRITE Cycles of Flash
Memory
– 10,000 Erase/WRITE Cycles of EEPROM
– 1,000 Erase/WRITE Cycles of PLD
– Data Retention: 15-year minimum at 90°C
(for Main Flash, Boot, PLD and
Configuration bits).
SINGLE SUPPLY VOLTAGE:
– 3.3V±10% for PSD813F1V
PROGRAMMABLE POWER MANAGEMENT
STANDBY CURRENT AS LOW AS 50µA
Packages are ECOPACK®
October 2008
Rev 4
This is information on a product still in production but not recommended for new designs.
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