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PDF PSD813F2V Data sheet ( Hoja de datos )
| Número de pieza | PSD813F2V | |
| Descripción | Flash in-system programmable (ISP) peripherals | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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PSD813F2V PSD854F2V
Flash in-system programmable (ISP) peripherals
for 8-bit MCUs, 3.3 V
NOT FOR NEW DESIGN
FEATURES SUMMARY
■ FLASH IN-SYSTEM PROGRAMMABLE (ISP)
PERIPHERAL FOR 8-BIT MCUS
Figure 1. Packages
■ DUAL BANK FLASH MEMORIES
– UP TO 2 Mbit OF PRIMARY FLASH
MEMORY (8 Uniform Sectors, 32K x8)
– UP TO 256 Kbit SECONDARY FLASH
MEMORY (4 Uniform Sectors)
PQFP52 (M)
– Concurrent operation: READ from one
)memory while erasing and writing the
t(sother
■ UP TO 256 Kbit of SRAM
uc■ 27 RECONFIGURABLE I/O PORTS
d■ ENHANCED JTAG SERIAL PORT
ro■ PLD WITH MACROCELLS
P– Over 3000 Gates of PLD: CPLD and
teDPLD
le– CPLD with 16 Output Macrocells (OMCs)
and 24 Input Macrocells (IMCs)
so– DPLD - user defined internal chip select
bdecoding
O■ 27 INDIVIDUALLY CONFIGURABLE I/O
-PORT PINS
)The can be used for the following functions:
t(s– MCU I/Os
c– PLD I/Os
du– Latched MCU address output
ro– Special function I/Os.
P– 16 of the I/O ports may be configured as
open-drain outputs.
te■ IN-SYSTEM PROGRAMMING (ISP) WITH
leJTAG
o– Built-in JTAG compliant serial port allows
s full-chip In-System Programmability
Ob– Efficient manufacturing allow easy
PLCC52 (J)
TQFP64 (U)
■ HIGH ENDURANCE:
– 100,000 Erase/WRITE Cycles of Flash
Memory
– 1,000 Erase/WRITE Cycles of PLD
product testing and programming
– 15 Year Data Retention
– Use low cost FlashLINK cable with PC
■ 3.3V±10% SINGLE SUPPLY VOLTAGE
■ PAGE REGISTER
– Internal page register that can be used to
expand the microcontroller address space
by a factor of 256
■ STANDBY CURRENT AS LOW AS 25µA
■ Packages are ECOPACK®
■ PROGRAMMABLE POWER MANAGEMENT
May 2009
Doc ID 10552 Rev 3
This is information on a product still in production but not recommended for new designs.
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PSD813F2V, PSD854F2V
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
APPENDIX A.PQFP52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
APPENDIX B.PLCC52 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
APPENDIX C.TQFP64 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Obsolete Product(s) - Obsolete Product(s)
Doc ID 10552 Rev 3
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5 Page 
PSD813F2V, PSD854F2V
Pin Name Pin Type
Description
Reset
48
I
Resets I/O Ports, PLD macrocells and some of the Configuration Registers. Must be Low
at Power-up.
These pins make up Port A. These port pins are configurable and can have the following
functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellAB0-7) outputs.
PA0 29
Inputs to the PLDs.
PA1 28
PA2 27
Latched address outputs (see Table 6).
PA3
PA4
PA5
25
24
23
I/O Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA in
burst mode.
PA6 22
PA7 21
As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.
roduct(s)PB0
PPB1
tePB2
lePB3
PB4
oPB5
sPB6
bPB7
Obsolete Product(s) - OPC0
D0/A16-D3/A19 in M37702M2 mode.
Peripheral I/O mode.
Note: PA0-PA3 can only output CMOS signals with an option for high slew rate. However,
PA4-PA7 can be configured as CMOS or Open Drain Outputs.
These pins make up Port B. These port pins are configurable and can have the following
functions:
7 MCU I/O – write to or read from a standard output or input port.
6
5 CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.
4
3
I/O Inputs to the PLDs.
2
52 Latched address outputs (see Table 6).
51
Note: PB0-PB3 can only output CMOS signals with an option for high slew rate. However,
PB4-PB7 can be configured as CMOS or Open Drain Outputs.
PC0 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC0) output.
20 I/O Input to the PLDs.
TMS Input2 for the JTAG Serial Interface.
This pin can be configured as a CMOS or Open Drain output.
PC1 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC1) output.
PC1
19 I/O Input to the PLDs.
TCK Input2 for the JTAG Serial Interface.
This pin can be configured as a CMOS or Open Drain output.
Doc ID 10552 Rev 3
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| PDF Descargar | [ Datasheet PSD813F2V.PDF ] | |
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