|
|
PDF ATxmega128D4 Data sheet ( Hoja de datos )
| Número de pieza | ATxmega128D4 | |
| Descripción | 8/16-bit Atmel XMEGA D4 Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ATxmega128D4 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
8/16-bit Atmel XMEGA D4 Microcontroller
ATxmega128D4 / ATxmega64D4 /
ATxmega32D4 / ATxmega16D4
Features
High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller
Nonvolatile program and data memories
16K - 128KBytes of in-system self-programmable flash
4K - 8KBytes boot section
1K - 2KBytes EEPROM
2K - 8KBytes internal SRAM
Peripheral Features
Four-channel event system
Four 16-bit timer/counters
Two timer/counters with 4 output compare or input capture channels
Two timer/counters with 2 output compare or input capture channels
High-resolution extensions on all timer/counters
Advanced waveform extension (AWeX) on one timer/counter
Two USARTs with IrDA support for one USART
Two two-wire interfaces with dual address match (I2C and SMBus compatible)
Two serial peripheral interfaces (SPIs)
CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3) generator
16-bit real time counter (RTC) with separate oscillator
One twelve-channel, 12-bit, 200ksps Analog to Digital Converter
Two Analog Comparators with window compare function, and current sources
External interrupts on all general purpose I/O pins
Programmable watchdog timer with separate on-chip ultra low power oscillator
QTouch® library support
Capacitive touch buttons, sliders and wheels
Special microcontroller features
Power-on reset and programmable brown-out detection
Internal and external clock options with PLL and prescaler
Programmable multilevel interrupt controller
Five sleep modes
Programming and debug interfaces
PDI (program and debug interface)
I/O and packages
34 Programmable I/O pins
44 - lead TQFP
44 - pad VQFN/QFN
49 - ball VFBGA
Operating voltage
1.6 – 3.6V
Operating frequency
0 – 12MHz from 1.6V
0 – 32MHz from 2.7V
Atmel-8135R-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–02/2015
1 page  
Figure 2-2. VFBGA Pinout
Top view
1234567
A
B
C
D
E
F
G
Bottom view
7654321
A
B
C
D
E
F
G
1234
5 67
A
PA3
AVCC
GND
PR1
PR0
PDI PE3
B
PA4
PA1
PA0
GND
RESET/PDI_CLK
PE2
VCC
C PA5 PA2 PA6 PA7
GND
PE1 GND
D PB1 PB2 PB3 PB0
GND
PD7 PE0
E GND GND PC3 GND PD4 PD5 PD6
F VCC PC0 PC4 PC6
PD0 PD1 PD3
G PC1 PC2 PC5 PC7
GND
VCC
PD2
XMEGA D4 [DATASHEET]
Atmel-8135R-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–02/2015
5
5 Page 
6.5 Program Flow
After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program
counter (PC) addresses the next instruction to be fetched.
Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole
address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general
data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After
reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the
I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be
accessed through the five different addressing modes supported in the AVR CPU.
6.6 Status Register
The status register (SREG) contains information about the result of the most recently executed arithmetic or logic
instruction. This information can be used for altering program flow in order to perform conditional operations. Note that
the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many
cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine nor restored when returning from an
interrupt. This must be handled by software.
The status register is accessible in the I/O memory space.
6.7 Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing
temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit
registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and
POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing
data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded
after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point
above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.
During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be
two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program
memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices
with more than 128KB of program memory, the return address is three bytes, and hence the SP is
decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the
RETI instruction, and from subroutine calls using the RET instruction.
The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one
when data is popped off the stack using the POP instruction.
To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts
for up to four instructions or until the next I/O memory write.
After reset the stack pointer is initialized to the highest address of the SRAM. See Figure 7-2 on page 15.
6.8 Register File
The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register
file supports the following input/output schemes:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
XMEGA D4 [DATASHEET]
Atmel-8135R-AVR-ATxmega16D4-32D4-64D4-128D4-Datasheet–02/2015
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ATxmega128D4.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ATxmega128D3 | 8/16-bit Atmel AVR XMEGA D3 Microcontroller | ATMEL Corporation |
| ATxmega128D4 | 8/16-bit Atmel XMEGA D4 Microcontroller | ATMEL Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |