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PDF AT89LP3240 Data sheet ( Hoja de datos )
| Número de pieza | AT89LP3240 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• 8-bit Microcontroller Compatible with MCS®51 Products
• Enhanced 8051 Architecture
– Single-clock Cycle per Byte Fetch
– Up to 20 MIPS Throughput at 20 MHz Clock Frequency
– Fully Static Operation: 0 Hz to 20 MHz
– On-chip 2-cycle Hardware Multiplier
– 16x16 Multiply–Accumulate Unit
– 256x8 Internal RAM
– 4096x8 Internal Extra RAM
– Up to 4KB Extended Stack in Extra RAM
– Dual Data Pointers
– 4-level Interrupt Priority
• Nonvolatile Program and Data Memory
– 32K/64K Bytes of In-System Programmable (ISP) Flash Program Memory
– 8K Bytes of Flash Data Memory
– Endurance: Minimum 100,000 Write/Erase Cycles
– Serial Interface for Program Downloading
– 64-byte Fast Page Programming Mode
– 256-Byte User Signature Array
– 2-level Program Memory Lock for Software Security
– In-Application Programming of Program Memory
• Peripheral Features
– Three 16-bit Enhanced Timer/Counters
– Two 8-bit PWM Outputs
– 4-Channel 16-bit Compare/Capture/PWM Array
– Enhanced UART with Automatic Address Recognition and Framing
Error Detection
– Enhanced Master/Slave SPI with Double-buffered Send/Receive
– Master/Slave Two-Wire Serial Interface
– Programmable Watchdog Timer with Software Reset
– Dual Analog Comparators with Selectable Interrupts and Debouncing
– 8-channel 10-bit ADC/DAC
– 8 General-purpose Interrupt Pins
• Special Microcontroller Features
– Two-wire On-chip Debug Interface
– Brown-out Detection and Power-on Reset with Power-off Flag
– Active-low External Reset Pin
– Internal RC Oscillator
– Low Power Idle and Power-down Modes
– Interrupt Recovery from Power-down Mode
• I/O and Packages
– Up to 38 Programmable I/O Lines
– 40-lead PDIP or 44-lead TQFP/PLCC or 44-pad VQFN/MLF
– Configurable I/O Modes
• Quasi-bidirectional (80C51 Style)
• Input-Only (Tristate)
• Push-pull CMOS Output
• Open-drain
• Operating Conditions
– 2.4V to 3.6V VDD Voltage Range
– -40° C to 85°C Temperature Range
– 0 to 20 MHz @ 2.4–3.6V
8-bit
Microcontroller
with 32K/64K
Bytes In-System
Programmable
Flash
AT89LP3240
AT89LP6440
3706C–MICRO–2/11
1 page  
AT89LP3240/6440
Table 1-1. AT89LP3240/6440 Pin Description
Pin Number
TQFP PLCC PDIP VQFN Symbol Type
17 23 20 17 GND
I
I/O
18 24 21 18 P2.0 I/O
O
I/O
19 25 22 19 P2.1 I/O
O
I/O
20
26
23
20
P2.1
I/O
O
O
I/O
21
27
24
21
P2.3
I/O
O
O
I/O
22 28 25 22 P2.4
I
O
I/O
23 29 26 23 P2.5
I
O
I/O
24 30 27 24 P2.6
I
O
I/O
25 31 28 25 P2.7
I
O
26 32 29 26 P4.5 I/O
27
33
30
27
P4.4
I/O
O
28 34
28 GND
I
I/O
29 35 31 29 P4.3 I/O
I/O
30 36 32 30 P0.7
O
I
I/O
31 37 33 31 P0.6
O
I
I/O
32 38 34 32 P0.5
O
I
I/O
33 39 35 33 P0.4
O
I
I/O
34 40 36 34 P0.3
O
I
Description
Ground
P2.0: User-configurable I/O Port 2 bit 0.
CCA: Timer 2 Channel A Compare Output or Capture Input.
A8: External memory interface Address bit 8.
P2.1: User-configurable I/O Port 2 bit 1.
CCB: Timer 2 Channel B Compare Output or Capture Input.
A9: External memory interface Address bit 9.
P2.2: User-configurable I/O Port 2 bit 2.
CCC: Timer 2 Channel C Compare Output or Capture Input.
A10: External memory interface Address bit 10.
DA-: DAC negative differential output.
P2.3: User-configurable I/O Port 2 bit 3.
CCD: Timer 2 Channel D Compare Output or Capture Input.
A11: External memory interface Address bit 11.
D+-: DAC positive differential output.
P2.4: User-configurable I/O Port 2 bit 5.
AIN0: Analog Comparator Input 0.
A12: External memory interface Address bit 12.
P2.5: User-configurable I/O Port 2 bit 5.
AIN1: Analog Comparator Input 1.
A13: External memory interface Address bit 13.
P2.6: User-configurable I/O Port 2 bit 6.
AIN2: Analog Comparator Input 2.
A14: External memory interface Address bit 14.
P2.7: User-configurable I/O Port 2 bit 7.
AIN3: Analog Comparator Input 3.
A15: External memory interface Address bit 15.
P4.5: User-configurable I/O Port 4 bit 5.
P4.4: User-configurable I/O Port 4 bit 4.
ALE: External memory interface Address Latch Enable.
Ground
P4.3: User-configurable I/O Port 4 bit 3.
DDA: Serial Data input/output for On-Chip Debug Interface when OCD is enabled and
the Crystal oscillator is selected as the clock source.
P0.7: User-configurable I/O Port 0 bit 7.
AD7: External memory interface Address/Data bit 7.
ADC7: ADC analog input 7.
P0.6: User-configurable I/O Port 0 bit 6.
AD6: External memory interface Address/Data bit 6.
ADC6: ADC analog input 6.
P0.5: User-configurable I/O Port 0 bit 5.
AD5: External memory interface Address/Data bit 5.
ADC5: ADC analog input 5.
P0.4: User-configurable I/O Port 0 bit 4.
AD4: External memory interface Address/Data bit 4.
ADC4: ADC analog input 4.
P0.3: User-configurable I/O Port 0 bit 3.
AD3: External memory interface Address/Data bit 3.
ADC3: ADC analog input 3.
3706C–MICRO–2/11
5
5 Page 
AT89LP3240/6440
3. Memory Organization
The AT89LP3240/6440 uses a Harvard Architecture with separate address spaces for program
and data memory. The program memory has a regular linear address space with support for 64K
bytes of directly addressable application code. The data memory has 256 bytes of internal RAM
and 128 bytes of Special Function Register I/O space. The AT89LP3240/6440 supports external
data memory with portions of the external data memory space implemented on chip as Extra
RAM and nonvolatile Flash data memory. External program memory is not supported. The mem-
ory address spaces of the AT89LP3240/6440 are listed in Table 3-1.
Table 3-1. AT89LP3240/6440 Memory Address Spaces
Name
Description
Range
DATA
Directly addressable internal RAM
00H–7FH
IDATA
Indirectly addressable internal RAM and stack space
00H–FFH
SFR
Directly addressable I/O register space
80H–FFH
EDATA
On-chip Extra RAM and extended stack space
0000H–0FFFH
FDATA
On-chip nonvolatile Flash data memory
1000H–2FFFH
XDATA
External data memory
3000H–FFFFH
CODE
On-chip nonvolatile Flash program memory (AT89LP3240)
On-chip nonvolatile Flash program memory (AT89LP6440)
0000H–7FFFH
0000H–FFFFH
SIG On-chip nonvolatile Flash signature array
0000H–01FFH
3.1 Program Memory
The AT89LP3240/6440 contains 32K/64K bytes of on-chip In-System Programmable Flash
memory for program storage. The Flash memory has an endurance of at least 100,000
write/erase cycles and a minimum data retention time of 10 years. The reset and interrupt vec-
tors are located within the first 83 bytes of program memory (refer to Table 9-1 on page 41).
Constant tables can be allocated within the entire 32K/64K program memory address space for
access by the MOVC instruction. The AT89LP3240/6440 does not support external program
memory. A map of the AT89LP3240/6440 program memory is shown in Figure 3-1.
3.1.1 SIG
In addition to the 64K code space, the AT89LP3240/6440 also supports a 256-byte User Signa-
ture Array and a 128-byte Atmel Signature Array that are accessible by the CPU. The Atmel
Signature Array is initialized with the Device ID in the factory. The second page of the User Sig-
nature Array (0180H–01FFH) is initialized with analog configuration data including the Internal
RC Oscillator calibration byte. The User Signature Array is available for user identification codes
or constant parameter data. Data stored in the signature array is not secure. Security bits will
disable writes to the array; however, reads by an external device programmer are always
allowed.
In order to read from the signature arrays, the SIGEN bit (DPCF.3) must be set (See Table 5-5
on page 28). While SIGEN is one, MOVC A,@A+DPTR will access the signature arrays. The
User Signature Array is mapped from addresses 0100h to 01FFh and the Atmel Signature Array
is mapped from addresses 0000h to 007Fh. SIGEN must be cleared before using MOVC to
access the code memory. The User Signature Array may also be modified by the In-Application
Programming interface. When IAP = 1 and SIGEN = 1, MOVX @DPTR instructions will access
the array (See Section 3.5 on page 21).
3706C–MICRO–2/11
11
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