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TH58NVG7T2ELA46 fiches techniques PDF

Toshiba - 128 GBIT (4G x 8 BIT x 4) CMOS NAND E2PROM

Numéro de référence TH58NVG7T2ELA46
Description 128 GBIT (4G x 8 BIT x 4) CMOS NAND E2PROM
Fabricant Toshiba 
Logo Toshiba 





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TH58NVG7T2ELA46 fiche technique
TOSHIBA CONFIDENTIAL TH58NVG7T2ELA46
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
128 GBIT (4G × 8 BIT x 4) CMOS NAND E2PROM (Multi-Level-Cell)
DESCRIPTION
The TH58NVG7T2E is a single 3.3 V 128 Gbit (145,572,102,144bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E2PROM) organized as (8192 + 376) bytes × 192 pages × 2780 blocks × 4.
The device has two 8568-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 8568-byte increments. The Erase operation is implemented in a single block
unit (1536 Kbytes + 70.5 Kbytes:8568 bytes x 192 pages).
The TH58NVG7T2E is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
Organization
Memory cell array
Register
Page size
Block size
TH58NVG7T2E
8568 × 521.3K × 8 x 4
8568 × 8
8568 bytes
(1536K + 70.5K) bytes
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Program, Multi Block Erase,Multi Page Copy, Mullti Page Read
Mode control
Serial input/output
Command control
Number of valid blocks
Min 10624 blocks
Max 11120 blocks
Power supply
VCC = 2.7 V to 3.6 V
VCCQ = 2.7 V to 3.6 V
Access time
Cell array to register 250 µs max
Serial Read Cycle
25 ns min
Program/Erase time
Auto Page Program
Auto Block Erase
2700 µs/page typ.
4 ms/block typ.
Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
60 mA max. (per 1chip)
60 mA max. (per 1chip)
60 mA max. (per 1chip)
400 µA max
Package
P – TLGA40 – 1317 – 1.04AZ (Weight: 0.46g typ.)
FOR RELIABILITY GUIDANCE, PLEASE REFER TO THE APPLICATION NOTES AND COMMENTS (17).
24 bit ECC for each 1K bytes is required.
1 2009-07-14C

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