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PDF MMDF2C02HD Data sheet ( Hoja de datos )
| Número de pieza | MMDF2C02HD | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MMDF2C02HD
Preferred Device
Power MOSFET
2 Amps, 20 Volts
Complementary SO−8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain−to−source diode has a very low reverse recovery time.
MiniMOSt devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dc−dc converters, and power management in portable
and battery powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor controls
in mass storage products such as disk drives and tape drives. The
avalanche energy is specified to eliminate the guesswork in designs
where inductive loads are switched and offer additional safety margin
against unexpected voltage transients.
• Ultra Low RDS(on) Provides Higher Efficiency and Extends
Battery Life
• Logic Level Gate Drive − Can Be Driven by Logic ICs
• Miniature SO−8 Surface Mount Package − Saves Board Space
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed, With Soft Recovery
• Avalanche Energy Specified
• Mounting Information for SO−8 Package Provided
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) (Note 1.)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Drain−to−Gate Voltage (RGS = 1.0 mΩ)
Drain Current − Continuous N−Channel
P−Channel
− Pulsed
N−Channel
P−Channel
VDSS
VGS
VDGR
ID
IDM
20
± 20
20
3.8
3.3
19
20
Vdc
Vdc
Vdc
A
Operating and Storage Temperature Range
TJ, Tstg − 55
to 150
°C
Total Power Dissipation @ TA= 25°C (Note 2.)
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 20 V, VGS = 5.0 V, Peak IL = 9.0 A,
L = 10 mH, RG = 25 Ω) N−Channel
(VDD = 20 V, VGS = 5.0 V, Peak IL = 6.0 A,
L = 18 mH, RG = 25 Ω) P−Channel
Thermal Resistance − Junction to Ambient
(Note 2.)
PD
EAS
RθJA
2.0 Watts
mJ
405
324
62.5 °C/W
Maximum Lead Temperature for Soldering,
TL 260 °C
0.0625″ from case. Time in Solder Bath is
10 seconds.
1. Negative signs for P−Channel device omitted for clarity.
2. Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided) with
one die operating, 10 sec. max.
http://onsemi.com
2 AMPERES
20 VOLTS
RDS(on) = 90 mW (N−Channel)
RDS(on) = 160 mW (P−Channel)
N−Channel
D
P−Channel
D
GG
SS
MARKING
DIAGRAM
8
SO−8, Dual
CASE 751
STYLE 14
D2C02
LYWW
1
D2C02 = Device Code
L = Location Code
Y = Year
WW = Work Week
PIN ASSIGNMENT
N−Source
N−Gate
P−Source
P−Gate
18
27
36
45
Top View
N−Drain
N−Drain
P−Drain
P−Drain
ORDERING INFORMATION
Device
Package
Shipping
MMDF2C02HDR2 SO−8 2500 Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 7
1
Publication Order Number:
MMDF2C02HD/D
1 page  
MMDF2C02HD
TYPICAL ELECTRICAL CHARACTERISTICS
N−Channel
P−Channel
0.6
ID = 1.5 A
TJ = 25°C
0.6
ID = 1 A
TJ = 25°C
0.4 0.4
0.2 0.2
0
0 1 2 3 4 5 6 7 8 9 10
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 3. On−Resistance versus
Gate−To−Source Voltage
0.08
TJ = 25°C
VGS = 4.5 V
0.07
0.06 10 V
0
02 4 6 8
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 3. On−Resistance versus
Gate−To−Source Voltage
0.20
TJ = 25°C
0.16 VGS = 4.5 V
0.12
10 V
0.08
10
0.05
0
1 2 34 5
ID, DRAIN CURRENT (AMPS)
6
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1.6
VGS = 10 V
1.4 ID = 1.5 A
1.2
1
0.8
0.6
−50
−25 0
25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
150
0.04
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1.6
VGS = 10 V
ID = 2 A
1.4
1.2
1.0
0.8
0.6
−50 − 25
0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance Variation with
Temperature
http://onsemi.com
5
5 Page 
MMDF2C02HD
INFORMATION FOR USING THE SO−8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self−align when
subjected to a solder reflow process.
0.060
1.52
0.275
7.0
0.155
4.0
0.024
0.6
0.050
1.270
inches
mm
SO−8 POWER DISSIPATION
The power dissipation of the SO−8 is a function of the
input pad size. This can vary from the minimum pad size
for soldering to the pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction
temperature of the die, RθJA, the thermal resistance from
the device junction to ambient; and the operating
temperature, TA. Using the values provided on the data
sheet for the SO−8 package, PD can be calculated as
follows:
PD =
TJ(max) − TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 2.0 Watts.
PD =
150°C − 25°C
62.5°C/W
= 2.0 Watts
The 62.5°C/W for the SO−8 package assumes the
recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 2.0 Watts using the
footprint shown. Another alternative would be to use a
ceramic substrate or an aluminum core board such as
Thermal Cladt. Using board material such as Thermal
Clad, the power dissipation can be doubled using the same
footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
* * Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
http://onsemi.com
11
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| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet MMDF2C02HD.PDF ] | |
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